参数资料
型号: PIC16F716-E/SO
厂商: Microchip Technology
文件页数: 126/136页
文件大小: 0K
描述: IC PIC MCU FLASH 2KX14 18SOIC
产品培训模块: Asynchronous Stimulus
标准包装: 42
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 13
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 18-SOIC(0.295",7.50mm 宽)
包装: 管件
配用: I3-DB16F716-ND - BOARD DAUGHTER ICEPIC3
AC162054-ND - HEADER INTERFACE ICD2 16F716
2007 Microchip Technology Inc.
DS41206B-page 7
PIC16F716
2.0
MEMORY ORGANIZATION
There are two memory blocks in the PIC16F716
device. Each block (program memory and data
memory) has its own bus so that concurrent access
can occur.
2.1
Program Memory Organization
The PIC16F716 has a 13-bit program counter capable
of addressing an 8K x 14 program memory space. The
PIC16F716 has 2K x 14 words of program memory.
Accessing a location above the physically implemented
address will cause a wrap-around.
The Reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK OF
PIC16F716
2.2
Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPR)
and the Special Function Registers (SFR). Bits RP1
and RP0 of the STATUS register are the bank select
bits.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers
are
General
Purpose
Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. The upper 16
bytes of GPR space and some “high use” Special
Function Registers in Bank 0 are mirrored in Bank 1 for
code reduction and quicker access.
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Use
rMe
mo
ry
Sp
ac
e
RP<1:0>(1)
(Status<6:5>)
Bank
00
0
01
1
10
2(2)
11
3(2)
Note 1: Maintain Status bit 6 clear to ensure
upward compatibility with future products.
2: Not implemented
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