参数资料
型号: PIC16F73-I/SO
厂商: Microchip Technology
文件页数: 71/104页
文件大小: 0K
描述: IC MCU FLASH 4KX14 A/D 28SOIC
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 27
系列: PIC® 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 22
程序存储器容量: 7KB(4K x 14)
程序存储器类型: 闪存
RAM 容量: 192 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 5.5 V
数据转换器: A/D 5x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 管件
产品目录页面: 640 (CN2011-ZH PDF)
配用: XLT28SO-1-ND - SOCKET TRANSITION 28SOIC 300MIL
Micrel, Inc.
KSZ8851-16MLLJ
March 2010
60
M9999-030210-1.0
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
Bit
Default Value
R/W
Description
15-13
-
RW
Reserved.
12
-
RO
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
11
-
RO
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
10
-
RO
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
9
0x0
RW
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable to add two bytes before
frame header in order for IP header inside the frame contents to be aligned with double
word boundary to speed up software operation.
8
-
RW
Reserved.
7
0x0
RW
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
6
0x0
RW
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the number of received bytes in RXQ buffer exceeds the threshold set in RX Data
Byte Count Threshold Register (0x8E, RXDBCT).
5
0x0
RW
RXFCTE RX Frame Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLLJ will enable RX interrupt (bit 13 in ISR)
when the number of received frames in RXQ buffer exceeds the threshold set in RX
Frame Count Threshold Register (0x9C, RXFCT).
4
0x0
RW
ADRFE Auto-Dequeue RXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLLJ will automatically enable RXQ frame
buffer dequeue. The read pointer in RXQ frame buffer will be automatically adjusted to
next received frame location after current frame is completely read by the host.
3
0x0
WO
SDA Start DMA Access
When this bit is written as 1, the KSZ8851-16MLLJ allows a DMA operation from the host
CPU to access either read RXQ frame buffer or write TXQ frame buffer with CSN and
RDN or WRN signals while the CMD pin is low. All registers access are disabled except
this register during this DMA operation.
This bit must be set to 0 when DMA operation is finished in order to access the rest of
registers.
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