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参数资料
| 型号： | PIC16LC556-04/SS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO20 |
| 封装： | 0.209 INCH, PLASTIC, SSOP-20 |
| 文件页数： | 43/104页 |
| 文件大小： | 697K |
| 代理商： | PIC16LC556-04/SS |
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1996 Microchip Technology Inc.
Preliminary
DS40143A-page 43
PIC16C55X
7.5
Interrupts
The PIC16C55X has 3 sources of interrupt:
External interrupt RB0/INT
TMR0 overow interrupt
PortB change interrupts (pins RB7:RB4)
The interrupt control register (INTCON) records
individual interrupt requests in ag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overow interrupt ags are contained in the
INTCON register.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
ag bits. The interrupt ag bit(s) must be cleared in
software
before
re-enabling
interrupts
to
avoid
RB0/INT recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 7-13).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt ag bits. The interrupt ag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
ag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1:
Individual interrupt ag bits are set
regardless
of
the
status
of
their
corresponding mask bit or the GIE bit.
2:
When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP in the cycle immediately following
the instruction which clears the GIE bit.
The interrupts which were ignored are
still pending to be serviced when the GIE
bit is set again.
FIGURE 7-12: INTERRUPT LOGIC
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
Wake-up
(If in SLEEP mode)
Interrupt
to CPU
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC16LC558-04/P | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LC558-04/SO | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LC558-04/SS | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LC558-04E/P | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC16LC558-04E/SO | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 13 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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