参数资料
型号: PIC16LC716-04I/P
厂商: Microchip Technology
文件页数: 67/106页
文件大小: 0K
描述: IC MCU OTP 2KX14 A/D PWM 18DIP
产品培训模块: Asynchronous Stimulus
标准包装: 25
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 13
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 18-DIP(0.300",7.62mm)
包装: 管件
2005 Microchip Technology Inc.
DS41106B-page 61
PIC16C712/716
9.10
Interrupts
The PIC16C712/716 devices have up to 7 sources of
interrupt. The Interrupt Control Register (INTCON)
records individual interrupt requests in flag bits. It also
has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector
immediately. Individual
interrupts
can
be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set,
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Registers, PIR1 and PIR2. The corre-
sponding interrupt enable bits are contained in Special
Function Registers, PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in Special Function
Register, INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
FIGURE 9-14:
INTERRUPT LOGIC
Note:
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
CCP1IF
CCP1IE
TMR2IF
TMR2IE
TMR1IF
TMR1IE
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in Sleep mode)
Interrupt to CPU
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