参数资料
型号: PIC18F2321-E/SS
厂商: Microchip Technology
文件页数: 36/110页
文件大小: 0K
描述: IC PIC MCU FLASH 4KX16 28SSOP
产品培训模块: Asynchronous Stimulus
标准包装: 47
系列: PIC® 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 25MHz
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,HLVD,POR,PWM,WDT
输入/输出数: 25
程序存储器容量: 8KB(4K x 16)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 512 x 8
电压 - 电源 (Vcc/Vdd): 4.2 V ~ 5.5 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
包装: 管件
2009 Microchip Technology Inc.
DS39689F-page 31
PIC18F2221/2321/4221/4321 FAMILY
3.4
RC Oscillator
For timing insensitive applications, the RC and RCIO
Oscillator modes offer additional cost savings. The
actual oscillator frequency is a function of several
factors:
supply voltage
values of the external resistor (REXT) and
capacitor (CEXT)
operating temperature
Given the same device, operating voltage, temperature
and component values, there will also be unit-to-unit
frequency variations. These are due to factors such as:
normal manufacturing variation
difference in lead frame capacitance between
package types (especially for low CEXT values)
variations within the tolerance of limits of REXT
and CEXT
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 3-5 shows how the R/C combination is
connected.
FIGURE 3-5:
RC OSCILLATOR MODE
The RCIO Oscillator mode (Figure 3-6) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 3-6:
RCIO OSCILLATOR MODE
3.5
PLL Frequency Multiplier
A Phase Locked Loop (PLL) circuit is provided as an
option for users who wish to use a lower frequency
oscillator circuit or to clock the device up to its highest
rated frequency from a crystal oscillator. This may be
useful for customers who are concerned with EMI due
to high-frequency crystals or users who require higher
clock speeds from an internal oscillator.
3.5.1
HSPLL OSCILLATOR MODE
The HSPLL mode makes use of the HS mode oscillator
for frequencies up to 10 MHz. A PLL then multiplies the
oscillator output frequency by 4 to produce an internal
clock frequency up to 40 MHz. The PLLEN bit is not
available when this mode is configured as the primary
clock source.
The PLL is only available to the crystal oscillator when
the FOSC<3:0> Configuration bits are programmed for
HSPLL mode (= 0110).
FIGURE 3-7:
HSPLLBLOCKDIAGRAM
3.5.2
PLL AND INTOSC
The PLL is also available to the internal oscillator block
when the internal oscillator block is configured as the
primary clock source. In this configuration, the PLL is
enabled in software and generates a clock output of up
to 32 MHz. The operation of INTOSC with the PLL is
OSC2/CLKO
CEXT
REXT
PIC18FXXXX
OSC1
FOSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 k
Ω ≤ REXT ≤ 100 kΩ
20 pF
≤ CEXT ≤ 300 pF
CEXT
REXT
PIC18FXXXX
OSC1
Internal
Clock
VDD
VSS
Recommended values: 3 k
Ω ≤ REXT ≤ 100 kΩ
20 pF
≤ CEXT ≤ 300 pF
I/O (OSC2)
RA6
MU
X
VCO
Loop
Filter
Crystal
Osc
OSC2
OSC1
PLL Enable
FIN
FOUT
SYSCLK
Phase
Comparator
HS Oscillator Enable
÷4
(from Configuration Register 1H)
HS Mode
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