- 您现在的位置：买卖IC网 > PDF目录11355 > PIC18F2480-E/SP (Microchip Technology)IC PIC MCU FLASH 8KX16 28DIP PDF资料下载
参数资料
| 型号： | PIC18F2480-E/SP |
| 厂商： | Microchip Technology |
| 文件页数： | 33/88页 |
| 文件大小： | 0K |
| 描述： | IC PIC MCU FLASH 8KX16 28DIP |
| 产品培训模块： | Asynchronous Stimulus PIC18 J Series MCU Overview |
| 标准包装： | 15 |
| 系列： | PIC® 18F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 25MHz |
| 连通性： | CAN，I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，HLVD，POR，PWM，WDT |
| 输入/输出数： | 25 |
| 程序存储器容量： | 16KB（8K x 16） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 768 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.2 V ~ 5.5 V |
| 数据转换器： | A/D 8x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 配用： | DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页当前第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页
2010 Microchip Technology Inc.
DS21801F-page 39
MCP2515
5.2
Synchronization
To compensate for phase shifts between the oscillator
frequencies of each of the nodes on the bus, each CAN
controller must be able to synchronize to the relevant
signal edge of the incoming signal. Synchronization is
the
process
by
which
the
DPLL
function
is
implemented.
When an edge in the transmitted data is detected, the
logic will compare the location of the edge to the
expected time (SyncSeg). The circuit will then adjust
the values of PS1 and PS2 as necessary.
There are two mechanisms used for synchronization:
1.
Hard synchronization
2.
Resynchronization
5.2.1
HARD SYNCHRONIZATION
Hard synchronization is only performed when there is a
recessive-to-dominant edge during a BUS IDLE
condition, indicating the start of a message. After hard
synchronization, the bit time counters are restarted with
SyncSeg.
Hard synchronization forces the edge that has
occurred to lie within the synchronization segment of
the
restarted
bit
time.
Due
to
the
rules
of
synchronization, if a hard synchronization occurs, there
will not be a resynchronization within that bit time.
5.2.2
RESYNCHRONIZATION
As a result of resynchronization, PS1 may be
lengthened or PS2 may be shortened. The amount of
lengthening or shortening of the phase buffer segments
has an upper-bound, given by the Synchronization
Jump Width (SJW).
The value of the SJW will be added to PS1 or
subtracted from PS2 (see Figure 5-3). The SJW
represents the loop filtering of the DPLL. The SJW is
programmable between 1 TQ and 4 TQ.
5.2.2.1
Phase Errors
The NRZ bit coding method does not encode a clock
into the message. Clocking information will only be
derived from recessive-to-dominant transitions. The
property which states that only a fixed maximum
number of successive bits have the same value (bit-
stuffing) ensures resynchronization to the bit stream
during a frame.
The phase error of an edge is given by the position of
the edge relative to SyncSeg, measured in TQ. The
phase error is defined in magnitude of TQ as follows:
e = 0 if the edge lies within SYNCSEG
e > 0 if the edge lies before the SAMPLE POINT
(TQ is added to PS1)
e < 0 if the edge lies after the SAMPLE POINT of
the previous bit (TQ is subtracted from PS2)
5.2.2.2
No Phase Error (e = 0)
If the magnitude of the phase error is less than or equal
to the programmed value of the SJW, the effect of a
resynchronization is the same as that of a hard
synchronization.
5.2.2.3
Positive Phase Error (e > 0)
If the magnitude of the phase error is larger than the
SJW and, if the phase error is positive, PS1 is
lengthened by an amount equal to the SJW.
5.2.2.4
Negative Phase Error (e < 0)
If the magnitude of the phase error is larger than the
resynchronization jump width and the phase error is
negative, PS2 is shortened by an amount equal to the
SJW.
5.2.3
SYNCHRONIZATION RULES
1.
Only recessive-to-dominant edges will be used
for synchronization.
2.
Only one synchronization within one bit time is
allowed.
3.
An edge will be used for synchronization only if
the value detected at the previous sample point
(previously read bus value) differs from the bus
value immediately after the edge.
4.
A transmitting node will not resynchronize on a
positive phase error (e > 0).
5.
If the absolute magnitude of the phase error is
greater than the SJW, the appropriate phase
segment will adjust by an amount equal to the
SJW.
相关PDF资料 |
PDF描述 |
|---|---|
| V375A36E600B3 | CONVERTER MOD DC/DC 36V 600W |
| VE-JWH-IX-F1 | CONVERTER MOD DC/DC 52V 75W |
| PIC18F4610-I/ML | IC MCU FLASH 32KX16 44QFN |
| V375A36E600B2 | CONVERTER MOD DC/DC 36V 600W |
| VE-JWF-IX-F4 | CONVERTER MOD DC/DC 72V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PIC18F2480-I/ML | 功能描述:8位微控制器 -MCU 16 KB 768 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC18F2480-I/SO | 功能描述:8位微控制器 -MCU 16 KB 768 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC18F2480-I/SP | 功能描述:8位微控制器 -MCU 16 KB 768 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC18F2480T-I/ML | 功能描述:8位微控制器 -MCU 16 KB 768 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| PIC18F2480T-I/SO | 功能描述:8位微控制器 -MCU 16 KB 768 RAM 25 I/O RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
发布紧急采购，3分钟左右您将得到回复。