参数资料
型号: PIC18F26J50T-I/SO
厂商: Microchip Technology
文件页数: 13/32页
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 28-SOIC
产品培训模块: PIC18 J Series MCU Overview
标准包装: 1,600
系列: PIC® XLP™ 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3.8K x 8
电压 - 电源 (Vcc/Vdd): 2.15 V ~ 3.6 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 20
2009 Microchip Technology Inc.
TABLE 5-4:
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: CONFIGURATION BITS AND
DEVICE IDs
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default/
Unprogrammed
Value(1)
300000h CONFIG1L
DEBUG
XINST
STVREN
PLLDIV2(3) PLLDIV1(3) PLLDIV0(3)
WDTEN
111- 1111
300001h CONFIG1H
(2)
(4)
CP0
CPDIV1(3)
CPDIV0(3)
---- 0111
300002h CONFIG2L
IESO
FCMEN
LPT1OSC
T1DIG
FOSC2
FOSC1
FOSC0
11-1 1111
300003h CONFIG2H
(2)
WDTPS3
WDTPS2
WDTPS1
WDTPS0
---- 1111
300004h CONFIG3L DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 DSWDTEN DSBOREN
RTCOSC DSWDTOSC
1111 1111
300005h CONFIG3H
(2)
MSSPMSK
IOL1WAY
---- 1--1
300006h CONFIG4L
WPCFG
WPEND
WPFP5
WPFP4
WPFP3
WPFP2
WPFP1
WPFP0
1111 1111
300007h CONFIG4H
(2)
—WPDIS
---- ---1
3FFFFEh DEVID1
DEV2
DEV1
DEV0
REV4
REV3
REV2
REV1
REV0
xxxx xxxx
3FFFFFh DEVID2
DEV10
DEV9
DEV8
DEV7
DEV6
DEV5
DEV4
DEV3
0100 00xx
Legend:
x = unknown, u = unchanged, - = unimplemented. Shaded cells are unimplemented, read as ‘0’.
Note
1:
Values reflect the unprogrammed state as received from the factory and following Power-on Resets. In all other Reset states, the
configuration bytes maintain their previously programmed states.
2:
The value of these bits in program memory should always be ‘1’. This ensures that the location is executed as a NOP if it is
accidentally executed.
3:
These bits are not implemented in PIC18F46J11 family devices.
4:
This bit should always be maintained at ‘0’.
TABLE 5-5:
PIC18F46J11 AND PIC18F46J50 FAMILY DEVICES: BIT DESCRIPTIONS
Bit Name
Configuration
Words
Description
DEBUG
CONFIG1L
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general purpose
I/O pins
0 = Background debugger enabled, RB6 and RB7 are dedicated to in-circuit debug
XINST
CONFIG1L
Enhanced Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
STVREN
CONFIG1L
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
PLLDIV<2:0>(3)
CONFIG1L
PLL Input Divider bits
Divider must be selected to provide a 4 MHz input into the 96 MHz PLL.
111 = No divide – oscillator used directly (4 MHz input)
110 = Oscillator divided by 2 (8 MHz input)
101 = Oscillator divided by 3 (12 MHz input)
100 = Oscillator divided by 4 (16 MHz input)
011 = Oscillator divided by 5 (20 MHz input)
010 = Oscillator divided by 6 (24 MHz input)
001 = Oscillator divided by 10 (40 MHz input)
000 = Oscillator divided by 12 (48 MHz input)
WDTEN
CONFIG1L
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
CP0(4)
CONFIG1H
Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is code-protected
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.
3: These bits are not implemented in PIC18F46J11 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
protection, perform an ICSP Bulk Erase operation.
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