参数资料
型号: PIC18F26J50T-I/SO
厂商: Microchip Technology
文件页数: 19/32页
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 28-SOIC
产品培训模块: PIC18 J Series MCU Overview
标准包装: 1,600
系列: PIC® XLP™ 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3.8K x 8
电压 - 电源 (Vcc/Vdd): 2.15 V ~ 3.6 V
数据转换器: A/D 10x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 26
2009 Microchip Technology Inc.
RTCOSC
CONFIG3L
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
DSWDTOSC
CONFIG3L
DSWDT Reference Clock Select bit
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSPMSK(1,2)
CONFIG3H
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
PLLSEL(5)
CONFIG3H
PLL Selection bit
1 = 4x PLL selected
0 = 96 MHz PLL selected
ADCSEL
CONFIG3H
ADC Mode Selection bit
1 = 10-Bit ADC mode selected
0 = 12-Bit ADC mode selected
IOL1WAY
CONFIG3H
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
unlock sequence has been completed
WPCFG
CONFIG4L
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and
WPFP<6:0> settings include the Configuration Words page
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
WPFP<6:0>
CONFIG4L
Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase-protected.
WPEND
CONFIG4H
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages, WPFP<6:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<6:0> are write/erase-protected
WPDIS
CONFIG4H
Write Protect Disable bit
1 = WPFP<6:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or
written
0 = WPFP<6:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the
selected region(s)
LS48MHZ(3)
CONFIG4H
System Clock Selection bit
1 = System clock is expected at 48 MHz, FS/LS USB CLKEN’s divide-by is set to 8
0 = System clock is expected at 24 MHz, FS/LS USB CLKEN’s divide-by is set to 4
DEV<2:0>
DEVID1
Device ID bits
Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.
REV<4:0>
DEVID1
Revision ID bits
Indicate the device revision.
DEV<10:3>
DEVID2
Device ID bits
Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
TABLE 5-7:
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.
3: These bits are not implemented in PIC18F47J13 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
protection, perform an ICSP Bulk Erase operation.
5: Not implemented on PIC18F47J53 family devices.
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