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参数资料
型号： PIC18F45J50T-I/ML
厂商： Microchip Technology
文件页数： 153/164页
文件大小： 0K
描述： IC PIC MCU FLASH 32KB 44-QFN
产品培训模块： PIC18 J Series MCU Overview
标准包装： 1,600
系列： PIC® XLP™ 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 48MHz
连通性： I²C，SPI，UART/USART，USB
外围设备： 欠压检测/复位，DMA，POR，PWM，WDT
输入/输出数： 34
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 3.8K x 8
电压 - 电源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
数据转换器： A/D 13x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-VQFN 裸露焊盘
包装： 带卷 (TR)
2011 Microchip Technology Inc.
DS39931D-page 89
PIC18F46J50 FAMILY
6.3.5.1
Context Defined SFRs
There are several registers that share the same
address in the SFR space. The register’s definition and
usage depends on the operating mode of its associated
peripheral. These registers are:
SSPxADD and SSPxMSK: These are two
separate hardware registers, accessed through a
single SFR address. The operating mode of the
MSSP modules determines which register is
being accessed. See Section 19.5.3.4 “7-Bit
Address Masking Mode”
for additional details.
PMADDRH/L and PMDOUT2H/L: In this case,
these named buffer pairs are actually the same
physical registers. The Parallel Master Port (PMP)
module’s operating mode determines what func-
tion the registers take on. See Section 11.1.2
“Data Registers”
for additional details.
TABLE 6-4:
REGISTER FILE SUMMARY (PIC18F46J50 FAMILY)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details
on Page:
TOSU
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000
69, 81
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000
69, 79
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000
69, 79
STKPTR
STKFUL
STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000
69, 79
PCLATU
—
—bit 21(1)
Holding Register for PC<20:16>
---0 0000
69, 79
PCLATH
Holding Register for PC<15:8>
0000 0000
69, 79
PCL
PC Low Byte (PC<7:0>)
0000 0000
69, 79
TBLPTRU
—
bit 21
Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
--00 0000
69, 112
TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000
69, 112
TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000
69, 112
TABLAT
Program Memory Table Latch
0000 0000
69, 112
PRODH
Product Register High Byte
xxxx xxxx
69, 113
PRODL
Product Register Low Byte
xxxx xxxx
69, 113
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
0000 000x
69, 117
INTCON2
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
1111 1111
69, 117
INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
1100 0000
69, 117
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
69, 98
POSTINC0
Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
69, 99
POSTDEC0
Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
69, 99
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
69, 99
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
69, 99
FSR0H
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000
69, 98
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx
69, 98
WREG
Working Register
xxxx xxxx
69, 81
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
69, 98
POSTINC1
Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
69, 99
POSTDEC1
Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
69, 99
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
70, 99
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
69, 99
Legend:
x
= unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Bold indicates shared access SFRs.
Note
1:
Bit 21 of the PC is only available in Serial Programming (SP) modes.
2:
Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled.
3:
The SSPxMSK registers are only accessible when SSPxCON2<3:0> = 1001.
4:
Alternate names and definitions for these bits when the MSSP module is operating in I2C Slave mode. See Section 19.5.3.2 “Address
Masking Modes”
for details.
5:
These bits and/or registers are only available on 44-pin devices; otherwise, they are unimplemented and read as ‘0’. Reset values are
shown for 44-pin devices.
6:
The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the same physical registers and addresses, but have
different functions determined by the module’s operating mode. See Section 11.1.2 “Data Registers” for more information.
7:
The TRISA6 and TRISA7 bits are only implemented when the pins are not configured for primary oscillator functions.
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