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型号： PIC18F45J50T-I/ML
厂商： Microchip Technology
文件页数： 55/164页
文件大小： 0K
描述： IC PIC MCU FLASH 32KB 44-QFN
产品培训模块： PIC18 J Series MCU Overview
标准包装： 1,600
系列： PIC® XLP™ 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 48MHz
连通性： I²C，SPI，UART/USART，USB
外围设备： 欠压检测/复位，DMA，POR，PWM，WDT
输入/输出数： 34
程序存储器容量： 32KB（16K x 16）
程序存储器类型： 闪存
RAM 容量： 3.8K x 8
电压 - 电源 (Vcc/Vdd)： 2.15 V ~ 3.6 V
数据转换器： A/D 13x10b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-VQFN 裸露焊盘
包装： 带卷 (TR)
PIC18F46J50 FAMILY
DS39931D-page 148
2011 Microchip Technology Inc.
10.6
PORTE, TRISE and LATE
Registers
Depending on the particular PIC18F46J50 family
device selected, PORTE is implemented in two
different ways.
For 44-pin devices, PORTE is a 3-bit wide port. Three
pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/
AN7/PMCS) are individually configurable as inputs or
outputs. These pins have Schmitt Trigger input buffers.
When selected as analog inputs, these pins will read as
‘0’s.
The corresponding Data Direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., put the corresponding output
driver in a High-Impedance mode). Clearing a TRISE
bit (= 0) will make the corresponding PORTE pin an
output (i.e., put the contents of the output latch on the
selected pin).
TRISE controls the direction of the RE pins, even when
they are being used as analog inputs. The user must
make sure to keep the pins configured as inputs when
using them as analog inputs.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
EXAMPLE 10-6:
INITIALIZING PORTE
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by setting bit, REPU (PORTE<6>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
POR. The integrated weak pull-ups consist of a semi-
conductor structure similar to, but somewhat different,
from a discrete resistor. On an unloaded I/O pin, the
weak pull-ups are intended to provide logic high indica-
tion, but will not necessarily pull the pin all the way to
VDD levels.
Note that the pull-ups can be used for any set of
features, similar to the pull-ups found on PORTB
Note:
PORTE is available only on 44-pin devices.
Note:
On a POR, RE<2:0> are configured as
analog inputs.
CLRF
LATE
;Initialize LATE output
;latch values
MOVLB
0x0F
;ANCON registers not
;in access bank
BSF
ANCON0,PCFG5
;RE0/AN5 as digital
BSF
ANCON0,PCFG6
;RE1/AN6 as digital
MOVLW
0x03
;Example value used to
;initialize data direction
MOVWF
TRISE
;RE0, RE1 as inputs
;RE2 as output
REGISTER 10-5:
PORTE REGISTER
R/W-0
U-0
R/W-0
RDPU
REPU
—
RE2
RE1
RE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RDPU:
PORTD Pull-up Enable bit
1
= PORTD pull-ups are enabled by individual TRIS values
0
= All PORTD pull-ups are disabled
bit 6
REPU:
PORTE Pull-up Enable bit
1
= PORTE pull-ups are enabled by individual TRIS values
0
= All PORTE pull-ups are disabled
bit 5-3
Unimplemented:
Read as ‘0’
bit 2-0
RE<2:0>:
PORTE Data Input bits
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