参数资料
型号: PIC18F46J50-I/PT
厂商: Microchip Technology
文件页数: 11/164页
文件大小: 0K
描述: IC PIC MCU FLASH 64KB 44-TQFP
产品培训模块: XLP Deep Sleep Mode
PIC18 J Series MCU Overview
PIC18F MPLAB® Starter Kit
8-bit PIC® Microcontroller Portfolio
标准包装: 160
系列: PIC® XLP™ 18F
核心处理器: PIC
芯体尺寸: 8-位
速度: 48MHz
连通性: I²C,SPI,UART/USART,USB
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 34
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 3.8K x 8
电压 - 电源 (Vcc/Vdd): 2.15 V ~ 3.6 V
数据转换器: A/D 13x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
产品目录页面: 657 (CN2011-ZH PDF)
配用: AC164330-ND - MODULE SKT FOR 44TQFP 18F45J10
PIC18F46J50 FAMILY
DS39931D-page 108
2011 Microchip Technology Inc.
7.4
Erasing Flash Program Memory
The minimum erase block is 512 words or 1024 bytes.
Only through the use of an external programmer, or
through ICSP control, can larger blocks of program
memory be bulk erased. Word erase in the Flash array
is not supported.
When initiating an erase sequence from the micro-
controller itself, a block of 1024 bytes of program
memory is erased. The Most Significant 12 bits of the
TBLPTR<21:10> point to the block being erased;
TBLPTR<9:0> are ignored.
The EECON1 register commands the erase operation.
The WREN bit must be set to enable write operations.
The FREE bit is set to select an erase operation. For
protection, the write initiate sequence for EECON2
must be used.
A long write is necessary for erasing the internal Flash.
Instruction execution is halted while in a long write
cycle. The long write will be terminated by the internal
programming timer.
7.4.1
FLASH PROGRAM MEMORY
ERASE SEQUENCE
The sequence of events for erasing a block of internal
program memory location is:
1.
Load Table Pointer register with the address of
the row being erased.
2.
Set the WREN and FREE bits (EECON1<2,4>)
to enable the erase operation.
3.
Disable interrupts.
4.
Write 0x55 to EECON2.
5.
Write 0xAA to EECON2.
6.
Set the WR bit; this will begin the erase cycle.
7.
The CPU will stall for the duration of the erase
for TIE (see Parameter D133B).
8.
Re-enable interrupts.
EXAMPLE 7-2:
ERASING FLASH PROGRAM MEMORY
MOVLW
CODE_ADDR_UPPER
; load TBLPTR with the base
MOVWF
TBLPTRU
; address of the memory block
MOVLW
CODE_ADDR_HIGH
MOVWF
TBLPTRH
MOVLW
CODE_ADDR_LOW
MOVWF
TBLPTRL
ERASE_ROW
BSF
EECON1, WREN
; enable write to memory
BSF
EECON1, FREE
; enable Erase operation
BCF
INTCON, GIE
; disable interrupts
Required
MOVLW
0x55
Sequence
MOVWF
EECON2
; write 0x55
MOVLW
0xAA
MOVWF
EECON2
; write 0xAA
BSF
EECON1, WR
; start erase (CPU stall)
BSF
INTCON, GIE
; re-enable interrupts
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