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参数资料
型号： PIC18F66K90T-I/MRRSL
厂商： Microchip Technology
文件页数： 29/110页
文件大小： 0K
描述： MCU 8BIT 64K FLASH 64-QFN
标准包装： 3,300
系列： PIC® XLP™ 18F
核心处理器： PIC
芯体尺寸： 8-位
速度： 64MHz
连通性： I²C，LIN，SPI，UART/USART
外围设备： 欠压检测/复位，LCD，POR，PWM，WDT
输入/输出数： 53
程序存储器容量： 64KB（32K x 16）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
数据转换器： A/D 16x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 64-VFQFN 裸露焊盘
包装： 带卷 (TR)
PIC18F47J53 FAMILY
DS39964B-page 476
Preliminary
2010 Microchip Technology Inc.
COMF
Complement f
Syntax:
COMF
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
f
dest
Status Affected:
N, Z
Encoding:
0001
11da
ffff
Description:
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
COMF
REG, 0, 0
Before Instruction
REG
=
13h
After Instruction
REG
=
13h
W=
ECh
CPFSEQ
Compare f with W, Skip if f = W
Syntax:
CPFSEQ
f {,a}
Operands:
0
f 255
a
[0,1]
Operation:
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
Status Affected:
None
Encoding:
0110
001a
ffff
Description:
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If ‘f’ = W, then the fetched instruction is
discarded and a NOP is executed
instead, making this a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
No
operation
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
CPFSEQ REG, 0
NEQUAL
:
EQUAL
:
Before Instruction
PC Address
=
HERE
W=
?
REG
=
?
After Instruction
If REG
=
W;
PC
=
Address (EQUAL)
If REG
W;
PC
=
Address (NEQUAL)
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