参数资料
型号: PIC32MX575F256L-80I/BG
厂商: Microchip Technology
文件页数: 13/64页
文件大小: 0K
描述: IC MCU 32BIT 256KB FLASH 121XBGA
特色产品: 32-Bit PIC? Microcontroller
PIC32 32-Bit MCU Families
标准包装: 184
系列: PIC® 32MX
核心处理器: MIPS32? M4K?
芯体尺寸: 32-位
速度: 80MHz
连通性: CAN,I²C,SPI,UART/USART,USB OTG
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
程序存储器容量: 256KB(256K x 8)
程序存储器类型: 闪存
RAM 容量: 64K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 3.6 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 121-TFBGA
包装: 托盘
产品目录页面: 650 (CN2011-ZH PDF)
PIC32MX
DS61145K-page 20
2007-2012 Microchip Technology Inc.
7.0
ENTERING 2-WIRE ENHANCED
ICSP MODE
To use the 2-wire PGEDx and PGECx pins for pro-
gramming, they must be enabled. Note that any pair of
programming pins available on a particular device may
be used, however, they must be used as a pair. PGED1
must be used with PGEC1, and so on.
The following steps are required to enter 2-wire
Enhanced ICSP mode:
1.
The MCLR pin is briefly driven high, then low.
2.
A 32-bit key sequence is clocked into PGEDx.
3.
MCLR is then driven high within a specified
period of time and held.
and Timing Requirements” for timing requirements.
The programming voltage applied to MCLR is VIH,
which is essentially VDD, in PIC32MX devices. There is
no minimum time requirement for holding at VIH. After
VIH is removed, an interval of at least P18 must elapse
before presenting the key sequence on PGEDx.
The key sequence is a specific 32-bit pattern: ‘0100
1101
0100
0011
0100
1000
0101
0000
’ (the
acronym ‘MCHP’, in ASCII). The device will enter
Program/Verify mode only if the key sequence is valid.
The MSb of the Most Significant nibble must be shifted
in first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
the 2-wire Enhanced ICSP interface is to be main-
tained. An interval of at least time P19 and P7 must
elapse before presenting data on PGEDx. Signals
appearing on PGEDx before P7 has elapsed will not be
interpreted as valid.
Upon successful entry, the programming operations
documented in subsequent sections can be performed.
While in 2-wire Enhanced ICSP mode, all unused I/Os
are placed in the high-impedance state.
FIGURE 7-1:
ENTERING ENHANCED ICSP MODE
Note:
If using the 4-wire JTAG interface, the
following procedure is not necessary.
MCLR
PGEDx
PGECx
VDD
P6
P14
b31
b30
b29
b28
b27
b2
b1
b0
b3
...
Program/Verify Entry Code = 0x4D434850
P1A
P1B
P18
P19
01
0
1
0
P7
VIH
P20
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