PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
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tributary. The reading of the FIFOs by an external microprocessor is usually
done in response to an interrupt, but polling is also supported.
On power up of the system, the receiver defaults to a disabled state. One must
use the RHDL Indirect Channel Data registers to program each tributary. The
configuration of each tributary is independent of all others. The RHDL Interrupt
Control register should then be initialized to enable the INTB output and to select
the FIFO buffer fill level at which an interrupt will be generated. The FIFO
threshold is a global setting optimized for a particular system by trading off
minimizing the number of interrupts against avoiding FIFO overflows.
When the receiver is first enabled to delineate packets, it will assume the link is
idle and immediately begin searching for flags. No bytes will be written into the
FIFO until a flag is recognized. This is also true after an abort is detected. If
packet delineation is disabled, all bytes are written raw into the FIFO.
When the last byte of a properly terminated packet is received, an interrupt is
generated. While the RDLC Status register is being read the PKIN bit will be
logic 1. This can be a signal to the external processor to empty the bytes
remaining in the FIFO or to just increment a number-of-packets-received count
and wait for the FIFO to fill to a programmable level. Once the RDLC Status
register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is
read immediately after the last packet byte is read from the FIFO, the PBS[2] bit
will be logic 1 and the CRC and non-integer byte status can be checked by
reading the PBS[1:0] bits.
When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must
be emptied to remove this source of interrupt.
The T1/E1 Receive HDLC processor (RHDL) can be used in a polled or interrupt
driven mode for the transfer of packet data. In the polled mode, the processor
controlling the RHDL must periodically read the RHDL Interrupt Status #1 register
to determine if any tributaries need processing. In the interrupt driven mode, the
processor controlling the RHDL uses the TE-32 INTB output and the TE-32
Master Interrupt Source registers to determine when to service the RHDL.
In the case of interrupt driven data transfer from the RHDL to the processor, the
INTB output of the TE-32 is connected to the interrupt input of the processor.
The processor interrupt service routine verifies what block generated the interrupt
by reading the TE-32 Master Interrupt Source register followed by the Master
Interrupt Source T1E1 register to determine if RHDL is the interrupt source.
Once it has identified that the RHDL has generated the interrupt, it processes the
data in the following order: