PRELIMINARY
PM4332 TE-32
DATA SHEET
PMC-2011402
ISSUE 1
HIGH DENSITY 32 CHANNEL T1/E1/J1 FRAMER
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR THE INTERNAL USE OF ITS CUSTOMERS
394
In synchronous mode, the T1 tributary mapping is fixed to that shown in Table 24
and rate justifications are not possible using the V3 octet. The clock rate
information within the link rate octet in the V4 location is not used in synchronous
mode.
E1 Tributary Mapping
Table 26 shows the format for mapping E1s within the SPE octets. The timeslots
and framing bits within each E1 are easily located within this mapping for
channelized E1 applications. It is acceptable for the framing bits to not carry
valid framing information on the system interface Add Bus since the TE-32 will
provide this information. Unframed E1s use the exact same format for mapping
32 E1s into the SBI except that the E1 tributaries need not align with the timeslot
locations associated with channelized E1 applications. The V1, V2 and V4 octets
are not used to carry E1 data and are either reserved or used for control
information across the interface. When enabled, the V4 octet carries clock phase
information across the SBI. The V1 and V2 octets are unused and should be
ignored by devices listening to the SBI bus. The V5 and R octets do not carry
any information and are fixed to a zero value. The V3 octet carries an E1 data
octet but only during rate adjustments as indicated by the V5 indicator signals,
SDV5 and SAV5, and payload signals, SDPL and SAPL. The PP octets carry
channel associated signaling phase information and E1 multiframe alignment.
TS#0 through TS#31 make up the E1 channel.
The V1, V2, V3 and V4 octets are fixed to the locations shown. All the other
octets, shown shaded for E1#1,1, float within the allocated columns maintaining
the same order and moving a maximum of one octet per 2KHz multi-frame. The
position of the floating E1 is identified via the V5 Indicator signals, SDV5 and
SAV5, which locate the V5 octet. When the E1 tributary rate is faster than the E1
tributary nominal rate, the E1 tributary is shifted ahead by one octet which is
compensated by sending an extra octet in the V3 location. When the E1 tributary
rate is slower than the nominal rate the E1 tributary is shifted by one octet which
is compensated by inserting a stuff octet in the octet immediately following the V3
octet and delaying the octet that was originally in that position.
For the system interface Drop Bus only, when the SYNCH_TRIB bit is set for a
tributary, the timeslot alignment is precisely as presented in Table 26.
Table 26
- E1 Framing Format
COL #
E1#1,1
#2,1-3,21
E1#1,1
#2,1-3,21
E1#1,1
#2,1-3,21
E1#1,1
#2,1-3,21
ROW #
1-18
19
20-81
82
83-144
145
146-207
208
209-270
1
Unused
V1
V1
V5
-
PP
-
TS#0
-
2
Unused
TS#1
-
TS#2
-
TS#3
-
TS#4
-