STANDARD PRODUCT
PMC-Sierra, Inc.
PM6344 EQUAD
PMC-951013
ISSUE 5
QUADRUPLE E1 FRAMER
13
Pin Name
Type
Pin No.
Function
RDN[1]
RDN[2]
RDN[3]
RDN[4] /
Input
3
6
9
12
Receive Digital Negative Line Pulse (RDN[4:1]). These
inputs are available when the EQUAD is configured to
receive dual-rail formatted data. The RDN[4:1] inputs
may be enabled for either RZ or NRZ waveforms. When
enabled for NRZ, these inputs may be enabled to be
sampled on the rising or falling edge of the
corresponding RCLKI[4:1]. When enabled for RZ, the
clocks are recovered from the corresponding RDP[4:1]
and RDN[4:1] inputs.
RLCV[1]
RLCV[2]
RLCV[3]
RLCV[4]
Receive Line Code Violation Indication (RLCV[4:1]).
When the EQUAD is configured to receive single-rail
data, this input may be enabled to be sampled on the
rising or falling edge of the corresponding RCLKI[4:1].
RCLKI[1]
RCLKI[2]
RCLKI[3]
RCLKI[4]
Input
4
7
10
13
Receive Line Clock Inputs (RCLKI[4:1]). Each input is
an externally recovered 2.048 MHz line clock that may
be enabled to sample the RDP[x] and RDN[x] inputs on
its rising or falling edge when the input format is
enabled for dual-rail NRZ; or to sample the RDD[x] and
RLCV[x] inputs on its rising or falling edge when the
input format is enabled for single-rail.
RCLKO[1]
RCLKO[2]
RCLKO[3]
RCLKO[4]
Output
87
88
91
92
Recovered PCM Clock Output (RCLKO[4:1]). Each
output signal is the recovered 2.048 MHz clock,
synchronized to the XCLK signal. Each RCLKO[x]
signal is recovered from the RDP[x] and RDN[x] inputs
(if the input format is dual-rail RZ) or from the RCLKI[x]
input (if the input format is NRZ).
When the ELST is by-passed or the RCLKOSEL
register bit is set, BRPCM[x] and BRSIG[x] are updated
on the falling edge of the associated RCLKO[x].
As an option, the digital attenuator's smooth 2.048 MHz
clock may be presented on RCLKO[x]. See the
Operations Section for details on this application.