S/UNI-ATLAS-3200 Telecom Standard Product Data Sheet
Preliminary
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use
Document ID: PMC-1990553, Issue 4
391
FIFO enable – this is a single bit which enables the FIFO (1) or disables the FIFO (0). When the
FIFO is disabled, it refuses to accept any data, but data can still be read from it. This bit is
specified in the FIFO indirect configuration register (FIFO_ENBL field). Unused PHYs should
be left disabled, and should have their FLUSH bit set. Only ATM PHYs should be enabled in the
Input and Output SDQs, and only packet PHYs should be enabled in the Bypass SDQ. A FIFO
should be disabled and emptied if it is to be reconfigured.
Starting from the FIFO pointer, a FIFO occupies the number of blocks specified by its FIFO size.
The user should not configure the FIFO pointers such that two FIFOs overlap. The user can,
however, have gaps between consecutive FIFOs. This is useful when the FIFO size needs to be
adjusted dynamically.
The following table illustrates the configuration for a typical case. This example involves 3 PHYs
that have a bandwidth of STS-12, and are allocated 24 blocks each. In addition, there are 1 STS-3
PHY with a FIFO size of 6 blocks, 6 STS-1 PHYs each with a FIFO size of 2 blocks, and 3 T1
PHYs each with a FIFO size of 1 block. The sum of all the blocks used in this example is 93,
which is less than the total number of blocks available, 96.
Table 51 SDQ-ATLAS Configuration Example
PHYID
Bandwidth
FIFO pointer
FIFO size (blocks)
FIFO size (cells)
0
STS-12
0
24
48
1
STS-12
24
24
48
3
STS-3
48
6
12
4
STS-1
54
2
4
5
STS-1
56
2
4
2
STS-12
58
24
48
6
STS-1
82
2
4
7
STS-1
84
2
4
8
STS-1
86
2
4
9
STS-1
88
2
4
12
T1
90
1
2
10
T1
91
1
2
15
T1
92
1
2
Blocks 93 to 95 are not used in this example. Potentially, users can configure three more 1-block
FIFOs, or one more 1-block FIFO and one more 2-block FIFO, or to enlarge PHY #15 to 4
blocks, and so on. Note that the FIFOs are not required to be adjacent to each other; gaps are
allowed between FIFOs. For example, PHY #10 could start at block 93.
The SDQ cannot detect errors due to user misconfiguration. If the user sets up FIFOs that overlap
each other, or start at an illegal FIFO position (e.g. a number greater than 95) or with an illegal
FIFO size (i.e. 0, 97-127), the results will be unpredictable.
In terms of the actual programming sequence for a given FIFO, the recommended sequence is as
follows: