
RELEASED
DATA SHEET
PM7382 FREEDM-32P256
ISSUE 3
PMC-2010333
FRAME ENGINE AND DATA LINK MANAGER 32P256
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PCI Offset
Register
0x004
FREEDM-32P256 Master Interrupt Enable
0x008
FREEDM-32P256 Master Interrupt Status
0x00C
FREEDM-32P256 Master Clock / Frame Pulse / BERT Activity
Monitor and Accumulation Trigger
0x010
FREEDM-32P256 Master Link Activity Monitor
0x014
FREEDM-32P256 Master Line Loopback #1
0x018
FREEDM-32P256 Master Line Loopback #2
0x01C
FREEDM-32P256 Reserved
0x020
FREEDM-32P256 Master BERT Control
0x024
FREEDM-32P256 Master Performance Monitor Control
0x028 - 0x07C
Reserved
0x080
GPIC Control
0x084 - 0x0FC
GPIC Reserved
0x100
RCAS Indirect Channel and Time-slot Select
0x104
RCAS Indirect Channel Data
0x108
RCAS Framing Bit Threshold
0x10C
RCAS Channel Disable
0x110 - 0x17C
RCAS Reserved
0x180 – 0x1FC RCAS Link #0 through #31 Configuration
0x200
RHDL Indirect Channel Select
0x204
RHDL Indirect Channel Data Register #1
0x208
RHDL Indirect Channel Data Register #2
0x20C
RHDL Reserved
0x210
RHDL Indirect Block Select
0x214
RHDL Indirect Block Data Register
0x218 - 0x21C
RHDL Reserved
0x220
RHDL Configuration
0x224
RHDL Maximum Packet Length
0x228 - 0x23C
RHDL Reserved