参数资料
型号: PPC5604BCLL64
厂商: Freescale Semiconductor
文件页数: 38/109页
文件大小: 0K
描述: MCU 32BIT 512K 64MHZ
标准包装: 90
系列: MPC56xx Qorivva
核心处理器: e200z0h
芯体尺寸: 32-位
速度: 64MHz
连通性: CAN,I²C,LIN,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 79
程序存储器容量: 512KB(512K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 16
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 28x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
MPC5604B/C Microcontroller Data Sheet, Rev. 11.1
Package pinouts and signal descriptions
Freescale Semiconductor
34
NOTE
RAM data retention is guaranteed with VDD_LV not below 1.08 V.
Table 13. Recommended operating conditions (5.0 V)
Symbol
Parameter
Conditions
Value
Unit
Min
Max
VSS
SR Digital ground on VSS_HV pins
—
0
V
VDD1
SR Voltage on VDD_HV pins with respect to
ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
VSS_LV3
SR Voltage on VSS_LV (low voltage digital
supply) pins with respect to ground (VSS)
—VSS0.1 VSS+0.1
V
VDD_BV4
SR Voltage on VDD_BV pin (regulator supply)
with respect to ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Relative to VDD VDD0.1 VDD+0.1
VSS_ADC
SR Voltage on VSS_HV_ADC (ADC reference)
pin with respect to ground (VSS
—VSS0.1 VSS+0.1
V
VDD_ADC5
SR Voltage on VDD_HV_ADC pin (ADC
reference) with respect to ground (VSS)
—4.5
5.5
V
Voltage drop2
3.0
5.5
Relative to VDD VDD0.1 VDD+0.1
VIN
SR Voltage on any GPIO pin with respect to
ground (VSS)
—VSS0.1
—
V
Relative to VDD
—VDD+0.1
IINJPAD
SR Injected input current on any pin during
overload condition
—
55
mA
IINJSUM
SR Absolute sum of all injected input currents
during overload condition
—
50
TVDD
SR VDD slope to ensure correct power up6
—
0.25
V/s
TA C-Grade Part
SR Ambient temperature under bias
fCPU 64 MHz
40
85
°C
TJ C-Grade Part
SR Junction temperature under bias
40
110
TA V-Grade Part
SR Ambient temperature under bias
40
105
TJ V-Grade Part
SR Junction temperature under bias
40
130
TA M-Grade Part
SR Ambient temperature under bias
40
125
TJ M-Grade Part
SR Junction temperature under bias
40
150
1 100 nF capacitance needs to be provided between each VDD/VSS pair.
2 Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain
analog electrical characteristics will not be guaranteed to stay within the stated limits.
3 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair.
4 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed
depending on external regulator characteristics).
5 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair.
6 Guaranteed by device validation
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