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| 型号： | PS200-I/SS |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO20 |
| 封装： | 5.30 MM, PLASTIC, MO-150, SSOP-20 |
| 文件页数： | 6/36页 |
| 文件大小： | 537K |
| 代理商： | PS200-I/SS |
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PS200
DS21891B-page 12
2005 Microchip Technology Inc.
2.5
Lithium Application
Figure 2-3 is an example of the PS200 in a synchro-
nous buck charger for Lithium Ion batteries. The sense
resistor (RSENSE) is in a low side configuration.
Refer to the Microchip web site (www.microchip.com)
for the latest Application Notes that reference this
theory of operation and component values.
FIGURE 2-3:
SWITCH MODE CHARGER CIRCUIT EXAMPLE
FOR
REVISION
HISTORY,
SEE
826216
CHANGE
LOG
PS200-
BASED
CHARGER
REFERENCE
DESI
GN
–
SYNCHRONOUS
BUCK
TOPOLOGY
R
SENSE
V
DD
C1
100
nF
R4
1.5K
R
IH
R
IL
1.00K
C
COMP
1
C
COMP
2
R
COMP
R8
10.0K
R5 10.0K
R9
10.0K
Ct
Rt
RV
DD
R
VL
R
OVL
R2
0
10.0K
R1
9
10.0K
GRNLED
REDLED
R2
1.5K
R1
0
1.5K
3
1
2
D6
BAT54
L1
C3
100
nF
R
OVP
R
VH
C
out
C
IN
C2
3
4.7
μF
C1
8
4.7
μF
5
4
1
2
3
6
7
8
Q1
V
DD
1
LED2
2
VIN
3
RESET
4
CT
RL
OUT
5
PH1
15
LOOPFBK
7
LOOP
IN
8
CT
RL
IN
9
LED1
10
HV
OUT
11
IFBINB
12
IFBINA
13
IFBOUT
14
PH2
6
CHGFBK
16
SHDN
17
T
/ID
19
VOVP
18
V
SS
20
+
-
OP2
-
OP1
+
CP2
PW
M
+
CP1
V
REF
S
HDN
U1
PS200
CN
CP
SP
SN
TP
TN
DAT
A
MCLR
COMG
1-W
IRE
COMM.
ACCESS
+-
POW
ER
SUPPLY
INPUT
+
-
CHARGER
OUT
PUT
(T
O
B
A
TTE
R
Y
)
T
H
ERM
IST
OR/ID
SUPPLY
MUST
BE
FUSED
OR
CURRENT
L
IMIT
ED
OVP
DIVIDER
V
IN
DIVIDER
CONNECT
IONS
R1
2
10.0K
Q4
2N7002
Q6
M
BT4401
RG1
D5
1N4148
RD1
Q3
R11
1.0M
5
4
1
2
3
6
7
8
Q2
Q7
M
BT4401
Q8
M
BT4403
RG2
R1
10.0K
C
IH
RV
DD
:
POW
ER
SUPPLY
DROPPING
RESISTOR
Rt/Ct/D6
PW
M
RAM
P
G
ENERAT
OR.
C
IN
/C
OUT
/L1/Q1/Q2:
SY
NCHRONOUS-BUCK
POW
ER
SECTION
Q3
--
REVERSE
CONDUCT
ION
BLOCKING
SW
IT
CH
Q1
IS
A
P-CHANNEL
MOSFET
,SELECT
ED
FOR
AN
OPT
IMUM
BALANCE
BET
W
EEN
SW
IT
CHING
SPEED
AND
LOW
Rdson.
Q2
IS
AN
N-CHANNEL,
LOGIC
LEVEL
DRIVE
(V
GS
=
5V)
M
O
SFET
,
W
IT
H
AN
INTEGRAT
ED
SCHOTT
K
Y
DIODE.
Q1
IS
SELECTED
FOR
LOW
Rdson,
TO
MINIMIZE
CONDUCTION
LOSSES
(SEPARAT
E
MOSFET
AND
SCHOTT
K
Y
DEVICES
CAN
ALSO
BE
USED).
THIS
DESIGN
IS
A
DUAL
LOOP
TOPOLOGY,
WITH
HARDWARE-BASED
CURRENT
FEEDBACK
CONTROL
AND
FIRMWARE-BASED
VOLTAGE
FEEDBACK
CONTROL.
>
HARDWARE
CONFIGURED
AS
A
CONSTANT-CURRENT
LOOP,
CONTROLLING
PWM.
>
FIRMWARE
SETS
CURRENT
LEVEL
BY
ADJUSTING
PWM
SIGNAL
AT
CTRL
OUT
.
>
FIRMWARE
ALSO
CONSTANTLY
MEAS
URES
VOLTAGE;
WHEN
VOLTAGE
SETPOINT
REACHED,
FIRMWARE
DYNAMICALLY
ADJUSTS
CURRENT
TO
MAINTAIN
CONSTANT
VOLTAGE.
COMPONENT
S
T
H
AT
DO
NOT
HAVE
A
NUM
ERICAL
VALUE
ASSOCIAT
ED
W
IT
H
T
H
EM
ARE
DEPENDENT
UPON
T
H
E
VOLT
AGE/CURRENT
SPECIFICAT
IONS
OF
T
H
E
PART
ICULAR
APPLICAT
ION.
CONSULT
MICROCHIP
FOR
GUIDANCE
IN
DEFINING
T
H
ESE
COM
PONENT
VALUES.
C9
470
nF
FIRMW
ARE
CURRENT
CONT
ROL
OUT
PUT
:
CT
RL
OUT
IS
COMPARE
OUT
PUT
,W
H
ICH
IS
A
FIRMW
A
RE
CONT
ROLLED
PW
M
T
H
AT
SET
S
CURRENT
LEVEL.
R5/R9/C9
SCALE
AND
FILT
ER
T
H
E
VOLT
AGE
FROM
CT
RL
OUT
,
FOR
APPLICAT
ION
T
O
OP1.
R5/R9/C9
FORM
A
LOW
-PASS
FILTER,
W
IT
H
A
T
IME
CONSTANT
OF
4.7
MILLISECONDS.
THIS
ALLOW
S
FIRMW
ARE
L
OOP
UPDATE
RAT
ES
OF
UP
T
O
50
T
IMES
A
SECOND.
OP2
IS
CURRENT
SENSE
AMP.
R
IH
,R
IL
,R
SENSE
DETERMINE
CURRENT
SIGNAL
SCALING.
C
IH
IS
USED
IN
SOME
APPLICATIONS
T
O
FILTER
NOISE/SPIKES
FROM
CURRENT
SENSE
SIGNAL
.
HARDW
ARE
FEEDBACK
T
O
PW
M:
OP1
IS
ERROR
AMP.
C
COMP
1/C
COMP
2/R
COMP
ARE
LOOP
COM
PENSAT
ION
COM
PONENT
S.
R
t/C
t/D
6
C
O
N
VER
T
PW
M
O
U
T
P
U
T
O
R
A
MP
W
AVEFO
R
M,
W
H
IC
H
IS
FED
BAC
K
T
O
C
P
2
AN
D
C
O
MPAR
ED
T
O
ER
R
O
R
AMP
SIGN
AL
T
O
DE
T
E
RM
IN
E
P
W
M
DUTY
C
Y
CLE
.
D
ISC
R
E
T
E
MOSFET
D
R
IVER
S:
R
G
x/R
D
1
VALU
ES
AR
E
D
EPEN
D
E
N
T
U
P
O
N
CHA
RA
CT
E
R
IS
T
ICS
OF
Q1
A
N
D
Q2
IF
SU
PPLY
VOLT
AGE
EX
C
EED
S
V
GS
RA
T
ING
OF
Q1,
A
ZEN
ER
D
IO
D
E
C
A
N
BE
PLAC
ED
IN
SER
IES
W
IT
H
T
H
E
D
R
AIN
OF
Q4,
T
O
LIMIT
V
GS
OF
Q1
T
O
A
SAFE
LEVEL.
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