参数资料
型号: PS501-I/SS
厂商: Microchip Technology
文件页数: 6/42页
文件大小: 0K
描述: IC FIELD REPROG BATT MGR 28SSOP
标准包装: 47
功能: 充电管理
电池化学: 锂离子(Li-Ion)、锂聚合物(Li-Pol)
电源电压: 5.6 V ~ 18 V
工作温度: -20°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 管件
PS501
2.4
Voltage Measurements
The EEPROM value PackResistance is used to
The A/D input channels for cell and pack voltage mea-
surements are the VC(1) to VC(4) pins. Measurements
are taken each measurement period when the A/D is
active. The maximum voltage at any V CELL x input pin is
19V absolute, but voltages above 18V are not sug-
gested. The individual cell voltages are measured with
an integration method to reduce any sudden spikes or
fluctuations. The A/D uses an 11-bit resolution mode
for these measurements.
Cell voltage inputs are read every measurement
period, which is approximately every 500 milliseconds.
This could be further extended by the use of Sample
mode, where A/D measurements are not activated
every measurement period, depending on the configu-
ration of SampleLimit and NSample values. (See
information.) For Li Ion, Li-based, or even Lead-Acid
applications, up to four (4) series cell voltages may be
monitored individually. The highest voltage cell of the
stack must be connected to VC(1).
For some applications, the actual cell stack arrange-
ment can be altered accordingly. The PS501 voltage
input pins (V CELL x pins) are capable of measuring up to
18V each. Therefore, cell arrangements can be com-
bined and the corresponding cell voltage thresholds
can be adjusted. For example, a 2-cell Li Ion pack could
actually be connected as a single 7.2V cell instead of
two 3.6V cells. The values for the cell voltages would all
be doubled, for example V CELL 1 would equal the sum
of two cells and only the VC(1) input pin would be used.
Each V CELL x input circuit contains an internal resistive
divider to reduce the external voltage input to a range
that the internal A/D circuit can accommodate (150 mV
maximum). These dividers are set based on a
maximum cell voltage of 4.5 volts. A range of 340 mV
with dividers, based on a maximum voltage of 20 volts,
is used for pack voltage.
The impedance at each V CELL x input is roughly
100 kOhms, but is only connected to ground (via the
V SSA pins) when the actual voltage measurement is
occurring. This corresponds to an insignificant amount
of capacity drained through this circuit during the brief
voltage measurement period, typically 45 ms every
500 ms.
compensate for additional resistance that should be
removed.
The equation for the compensation value (in ohms) is:
EQUATION 2-3:
PackResistance = Trace Resistance * 65535
(This is a 2-byte value so the largest value is
1 ohm.)
This requires modification of overall voltage SBData
function to compensate for pack resistance and shunt
resistance of the current sense resistor. Thus, the
previous voltage equation is modified to:
EQUATION 2-4:
SBData Voltage Value = VC(1) + Measured
Current (mA) * PackResistance /65535
The voltage measurement equation is:
EQUATION 2-5:
V (mV) = (V_A/D – COVPack ) x CFVPack /16384
where:
V_A/D is the internal measurement output
COVPack is the “Correction Offset for Pack Voltage”
which compensates for any offset error in voltage mea-
surement (since the offset of the A/D is less than the
voltage measurement resolution of +/- 16.5 mV, the
COVPack value is typically zero).
CFVPack is the “Correction Factor for Pack Voltage”
which compensates for any variance in the actual A/D
response versus an ideal A/D response over varying
voltage inputs.
The COVPack and CFVPack are calibration constants
that are stored in EEPROM.
V CELL 1 and V CELL 4 can also be compensated for
impedance in the lines connecting to the PS501.
VC1Res is the resistance between the PS501 and the
highest series cell. VC4Res is the resistance between
the PS501 and the lowest cell. This allows the PS501
2.4.1
IMPEDANCE COMPENSATION
to subtract any voltage drop due to current between the
cell and the PS501.
Since accurate measurement of pack voltage and cell
voltages are critical to performance, the voltage
measurements can be compensated for any imped-
ance in the power path that might affect the voltage
measurements.
DS21818C-page 6
? 2004 Microchip Technology Inc.
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