参数资料
| 型号： | PS700T-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 27/38页 |
| 文件大小： | 0K |
| 描述： | IC BATT MONITOR 1-2CELL 8TSSOP |
| 标准包装： | 1 |
| 功能： | 电池监控器 |
| 电池化学： | 锂离子（Li-Ion） |
| 电源电压： | 2.7 V ~ 9 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 剪切带 (CT) |
| 其它名称： | PS700T-I/STCT |
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PS700
4.5
Power-on Reset
4.6
Factory Register Initialization
When power is first applied to the VC1 input, the PS700
automatically executes a Power-on Reset sequence.
The device is held in a Reset state while the voltage is
below the minimum operating threshold, V POR . When
the voltage on the VC1 input rises above the V POR
threshold, the PS700 will initialize itself as described
below. When initialization is complete, the PS700 will
enter Run mode.
During the Power-on Reset sequence, the registers are
loaded with initial values from EEPROM locations
0x020-0x087. These locations are reserved to contain
register initialization values. In a battery pack applica-
tion, a Power-on Reset typically happens only at the
time of pack manufacture, when the cells are first con-
nected to the battery monitoring pcb containing the
PS700.
Data in the EEPROM locations, (Bank 0) 0:0x020-
0:0x07F, will be loaded into the corresponding register
locations in (Bank 1) 1:0x020-1:0x07F. Data in the
EEPROM locations, (Bank 1) 0:0x080-0:0x084, will be
loaded into the corresponding Cal/Setup register loca-
tions in (Bank 2) 2:0x080-2:0x084. In all cases,
EEPROM register initialization locations corre-
sponding to “Reserved” register locations must
contain the value of 0x00h in order to insure proper
operation following a Power-on Reset.
The EEPROM register initialization locations are pro-
grammed with a set of default values at the time that
the PS700 is manufactured. This programming results
in the following general operational state of a PS700
following a Power-on Reset:
? All accumulators and time counters disabled and
reset to ‘ 0 ’
? All A/D conversion disabled
? A/D registers programmed with their anticipated
input source, resolution and input reference
? Sample and Shelf-Sleep modes disabled
? All Sample-Sleep mode entry methods disabled
and trip point values zeroed
? GPIO inputs on VC2 and NTC disabled
? SMBus address = 0x16
? Factory calibrated trim values for band gap,
voltage reference, auxiliary oscillator and main
oscillator
into the EEPROM register initialization locations.
Note:
Do not overwrite the factory trimmed
values.
? 2004 Microchip Technology Inc.
DS21760F-page 27
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