参数资料
型号: PSD8133V12JT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 93/110页
文件大小: 1685K
代理商: PSD8133V12JT
93/110
PSD813F1
Table 58. WRITE Timing (3V devices)
Note: 1. Any input used to select an internal PSD function.
2. In multiplexed mode, latched address generated from ADIO delay to address output on any port.
3. WR has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. TWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
Table 59. Flash Program, WRITE and Erase Times (5V devices)
Symbol
Parameter
Note: 1. Programmed to all zero before erase.
2. The polling status, DQ7, is valid t
Q7VQV
time units before the data byte, DQ0-DQ7, is valid for reading.
Symbol
Parameter
Conditions
-15
-20
Unit
Min
Max
Min
Max
t
LVLX
ALE or AS Pulse Width
26
30
t
AVLX
Address Setup Time
(Note
1
)
10
12
ns
t
LXAX
Address Hold Time
(Note
1
)
12
14
ns
t
AVWL
Address Valid to Leading
Edge of WR
(Notes
1,3
)
20
25
ns
t
SLWL
CS Valid to Leading Edge of WR
(Note
3
)
20
25
ns
t
DVWH
WR Data Setup Time
(Note
3
)
45
50
ns
t
WHDX
WR Data Hold Time
(Note
3
)
8
10
ns
t
WLWH
WR Pulse Width
(Note
3
)
48
53
ns
t
WHAX1
Trailing Edge of WR to Address Invalid
(Note
3
)
12
17
ns
t
WHAX2
Trailing Edge of WR to DPLD Address Invalid
(Note
3,6
)
0
0
ns
t
WHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note
3
)
45
50
ns
t
DVMV
Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear
(Notes
3,5
)
90
100
ns
t
AVPV
Address Input Valid to Address
Output Delay
(Note
2
)
48
55
ns
t
WLMV
WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear
(Notes
3,4
)
90
100
ns
Min.
Typ.
Max.
Unit
Flash Program
8.5
s
Flash Bulk Erase
1
(pre-programmed)
3
30
s
Flash Bulk Erase (not pre-programmed)
10
s
t
WHQV3
Sector Erase (pre-programmed)
1
30
s
t
WHQV2
Sector Erase (not pre-programmed)
2.2
s
t
WHQV1
Byte Program
14
1200
μs
Program / Erase Cycles (per Sector)
100,000
cycles
t
WHWLO
Sector Erase Time-Out
100
μs
t
Q7VQV
DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)
2
30
ns
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