参数资料
型号: PSD8134V20JT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 37/110页
文件大小: 1685K
代理商: PSD8134V20JT
37/110
PSD813F1
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate 3 external chip selects,
routed to Port D.
Although external chip selects can be produced by
any Output Macrocell, these three external chip
selects on Port D do not consume any Output
macrocells.
As shown in
Figure 15., page 35
, the CPLD has
the following blocks:
24 Input macrocells (IMCs)
16 Output macrocells (OMCs)
Macrocell Allocator
Product Term Allocator
I
I
I
I
I
AND array capable of generating up to 137
product terms
Four I/O ports.
Each of the blocks are described in the subsec-
tions that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the microcontrol-
ler. This enables the MCU software to load data
into the Output Macrocells (OMC) or read data
from both the Input and Output Macrocells (IMC
and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND logic array as required in
most standard PLD macrocell architectures.
I
Figure 17. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
M
M
M
M
D
D
Q
Q
Q
G
D
Q D
WR
WR
PDR
DATA
PALLOCATOR
DIR
SELECT
INPUT
PFROM OTHER
MACROCELLS
POLARITY
PROUP TO 10
CLOCK
PR
DI LD
D/T
CK
CL
Q
SELECT
PT CLEAR
PT
GLOBAL
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET
MCU DATA IN
/REG
SELECT
MACTO
IALLOC.
OCPLD
TO OTHER I/O PORTS
P
P
MCU ADDRESS / DATA BUS
MOUT TO
MCU
CDATA
A
CPLD OUTPUT
I/O PIN
AI02874
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