参数资料
型号: PSD8134V20JT
厂商: 意法半导体
英文描述: Flash In-System Programmable ISP Peripherals For 8-bit MCUs
中文描述: Flash在系统可编程ISP的外设的8位微控制器
文件页数: 52/110页
文件大小: 1685K
代理商: PSD8134V20JT
PSD813F1
52/110
I/O PORTS
There are four programmable I/O ports: Ports A, B,
C, and D. Each of the ports is eight bits except Port
D, which is 3 bits. Each port pin is individually user
configurable, thus allowing multiple functions per
port. The ports are configured using PSDsoft Ex-
press Configuration or by the MCU writing to on-
chip registers in the CSIOP address space.
The topics discussed in this section are:
General Port architecture
Port Operating Modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port Functionality.
General Port Architecture
The general architecture of the I/O Port is shown
in
Figure 27., page 53
. Individual Port architec-
tures are shown in
Figure 29., page 60
to
Figure
32., page 63
. In general, once the purpose for a
port pin has been defined, that pin will no longer be
available for other purposes. Exceptions will be
noted.
As shown in
Figure 27., page 53
, the ports contain
an output multiplexer whose selects are driven by
the configuration bits in the Control Registers
(Ports A and B only) and PSDsoft Express Config-
uration. Inputs to the multiplexer include the fol-
lowing:
Output data from the Data Out Register
Latched address outputs
CPLD Macrocell output
External Chip Select from CPLD.
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
PDB is connected to the Internal Data Bus for
feedback and can be read by the microcontroller.
The Data Out and Macrocell outputs, Direction
and Control Registers, and port pin input are all
connected to the PDB.
I
I
I
I
I
I
I
I
I
The Port pin
s tri-state output driver enable is con-
trolled by a two input OR gate whose inputs come
from the CPLD AND array enable product term
and the Direction Register. If the enable product
term of any of the array outputs are not defined
and that port pin is not defined as a CPLD output
in the PSDabel file, then the Direction Register has
sole control of the buffer that drives the port pin.
The contents of these registers can be altered by
the microcontroller. The PDB feedback path al-
lows the microcontroller to check the contents of
the registers.
Ports A, B, and C have embedded Input Macro-
cells (IMCs). The IMCs can be configured as latch-
es, registers, or direct inputs to the PLDs. The
latches and registers are clocked by the address
strobe (AS/ALE) or a product term from the PLD
AND array. The outputs from the IMCs drive the
PLD input bus and can be read by the microcon-
troller.
See
the
section
Macrocell, page 42
.
Port Operating Modes
The I/O Ports have several modes of operation.
Some modes can be defined using PSDabel,
some by the microcontroller writing to the Control
Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft Ex-
press must be programmed into the device and
cannot be changed unless the device is repro-
grammed. The modes that can be changed by the
microcontroller can be done so dynamically at run-
time. The PLD I/O, Data Port, Address Input, and
Peripheral I/O modes are the only modes that
must be defined before programming the device.
All other modes can be changed by the microcon-
troller at run-time.
Table 19., page 54
summarizes which modes are
available on each port.
Table 22., page 57
shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following subsections.
entitled
Input
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