参数资料
型号: PSD813F4-15JI
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
封装: PLASTIC, LCC-52
文件页数: 8/103页
文件大小: 1180K
代理商: PSD813F4-15JI
PSD8XXF2/3/4/5
12/103
JTAG Port
In-System Programming (ISP) can be performed
through the JTAG signals on Port C. This serial in-
terface allows complete programming of the entire
PSD8XXFX device. A blank device can be com-
pletely programmed. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be multi-
plexed with other functions on Port C. Table 3 in-
dicates the JTAG pin assignments.
In-System Programming (ISP)
Using the JTAG signals on Port C, the entire
PSD8XXFX device can be programmed or erased
without the use of the MCU. The primary Flash
memory can also be programmed in-system by
the MCU executing the programming algorithms
out of the secondary memory, or SRAM. The sec-
ondary memory can be programmed the same
way by executing out of the primary Flash memo-
ry. The PLD or other PSD8XXFX Configuration
blocks can be programmed through the JTAG port
or a device programmer. Table 4 indicates which
programming methods can program different func-
tional blocks of the PSD8XXFX.
Power Management Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
mode that helps reduce power consumption.
The PSD8XXFX also has some bits that are con-
figured at run-time by the MCU to reduce power
consumption of the CPLD. The Turbo bit in
PMMR0 can be reset to 0 and the CPLD latches its
outputs and goes to sleep until the next transition
on its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. Please see the sec-
tion entitled “POWER MANAGEMENT” on page
58 for more details.
Table 3. JTAG SIgnals on Port C
Table 4. Methods of Programming Different Functional Blocks of the PSD8XXFX
Port C Pins
JTAG Signal
PC0
TMS
PC1
TCK
PC3
TSTAT
PC4
TERR
PC5
TDI
PC6
TDO
Functional Block
JTAG Programming
Device Programmer
IAP
Primary Flash Memory
Yes
Secondary Flash Memory
Yes
PLD Array (DPLD and CPLD)
Yes
No
PSD8XXFX Configuration
Yes
No
相关PDF资料
PDF描述
PSD813F4-15J 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQCC52
PSD813F4-70M 128K X 8 FLASH, 27 I/O, PIA-GENERAL PURPOSE, PQFP52
PIC16C57C-04E/SS 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
PIC16LC55A-04/SP 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDIP28
PIC16LC57CT-04/SS 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO28
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