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参数资料
| 型号： | PSD935G2V-C-90U |
| 厂商： | 意法半导体 |
| 英文描述： | Configurable Memory System on a Chip for 8-Bit Microcontrollers |
| 中文描述： | 在8片位微控制器可配置存储系统 |
| 文件页数： | 50/91页 |
| 文件大小： | 488K |
| 代理商： | PSD935G2V-C-90U |
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PSD935G2
PSD9XX Family
49
The
PSD935G2
Functional
Blocks
(cont.)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address
input can be latched by the address strobe (ALE/AS). Any input that is included in the
DPLD equations for the Main Flash, Boot Flash, or SRAM is considered to be an address
input.
9.4.2.5 Data Port Mode
Port F can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port F if the port is configured as Data Port. Data Port
Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is selected.
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a ‘1’ for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 18 for the address output pin assignments on
Ports E, F and F for various MCUs.
Note:
Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
MCU
Port E (3:0)
Port E (7:4)
Port F (3:0)
Port F (7:4)
Port G (3:0)
Port G (7:4)
80C51XA
N/A
*
Addr (7:4)
N/A
*
Addr (7:4)
Addr (11:8)
N/A
80C251
(Page Mode)
N/A
N/A
N/A
N/A
Addr (11:8)
Addr (15:12)
All Other
Eight-Bit
Multiplexed
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
8-Bit
Non-Mux
Bus
N/A
N/A
N/A
N/A
Addr (3:0)
Addr (7:4)
Table 18. I/OPort Latched Address Output Assignments
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