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参数资料
| 型号： | PUMA68F32006M-90E |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 5V PROM MODULE, 90 ns, PQMA68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 11/23页 |
| 文件大小： | 181K |
| 代理商： | PUMA68F32006M-90E |
19
PUMA 68F32006/A-90/12/15
Issue 4.2 : December 1999
D7 Data Polling
During the Embedded Programming Algorithm, an attempt to read the device will produce the complement of
the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the
device will produce the true data last written to D7.
The device features Data Polling as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device
will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is
completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the
Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip erase,
the Toggle bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector
Erase, the toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active
during the sector time-out.
D6
Toggle Bit
The device also features the "toggle bit" as a method to indicate to the host system that the Embedded
Algorithms are in progress or completed.
D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will
produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only
operating function of the device under this condition. The CE circuit will partially power down the device under
these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions .
The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In
this case the device locks out and never completes the embedded algorithm operation. Hence the system
never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the
D5 bit will indicate '1'
D5 Exceeding Time Limits
After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3
will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may
be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase
cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase opera-
tion is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional
sector erase commands. To insure the command has been accepted, the software should check the status of
D3 prior to and following each subsequent sector erase command. If D3 were high on the second status
check, the command may not have been accepted.
D3
Sector Erase Timer
During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion
data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE
pulse.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, Erase Suspend, Erase-Suspend-Program, or sector erase time-out.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PUMA68F32006X-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| PUMA68F32006X-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| PUMA68F32006X-90 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| PUMA68F32006XI-12 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
| PUMA68F32006XI-15 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
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