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参数资料
| 型号： | QL5432-33APB456C |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 15/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APB456C |
15
QL5432 - QuickPCI
TM
Pin/Bus Name
Type
Function
AD[31:0]
CBEN[3:0]
T/S
T/S
PCI Address and Data: 32 bit multiplexed address/data bus.
PCI Bus Command and Byte Enables: Multiplexed bus which contains byte
enables for AD[31:0] or the Bus Command during the address phase of a
PCI transaction.
PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven
one clock after address or data phases. Master drives PAR on address cycles
and PCI writes. The Target drives PAR on PCI reads.
PCI Cycle Frame: Driven active by current PCI Master during a PCI transac-
tion. Driven low to indicate the address cycle, driven high at the end of the
transaction.
PCI Device Select. Driven by a Target that has decoded a valid base address.
PCI System Clock Input.
PCI System Reset Input
PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) wishes to
use the bus. A point to point signal between the PCI Device and the System
Arbiter.
PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access
to the PCI bus by the Arbiter. A point to point signal between the PCI device
and the System Arbiter.
PCI Data Parity Error. Driven active by the initiator or target two clock cycles
after a data parity error is detected on the AD and C/BE# busses.
PCI System Error: Driven active when an address cycle parity error, data par-
ity error during a special cycle, or other catastrophic error is detected.
PCI Initialization Device Select. Use to select a specific PCI Agent during
System Initialization.
PCI Initiator Ready. Indicates the Initiator’s ability to complete a read or
write transaction. Data transfer occurs only on clock cycles where both
IRDYN and TRDYN are active.
PCI Target Ready. Indicates the Target’s ability to complete a read or write
transaction. Data transfer occurs only on clock cycles where both IRDYN
and TRDYN are active.
PCI Stop. Used by a PCI Target to end a burst transaction.
Interrupt A. Asynchronous Active-Low Interrupt Request.
PAR
T/S
FRAMEN
S/T/S
DEVSELN
CLK
RSTN
REQN
S/T/S
IN
IN
T/S
GNTN
IN
PERRN
S/T/S
SERRN
O/D
IDSEL
IN
IRDYN
S/T/S
TRDYN
S/T/S
STOPN
INTAN
S/T/S
O/D
QL5432 External Device Pins
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相关代理商/技术参数 |
参数描述 |
|---|---|
| QL5432-33APQ208C-5846 | 制造商:QuickLogic Corporation 功能描述: |
| QL55M6XD30BQ | 制造商:Banner Engineering 功能描述:QL55M6XD30BQ LUMINESCENCE NPN/PNP M12 20 TO 40mm |
| QL55M6XD50BQ | 制造商:Banner Engineering 功能描述:QL55M6XD50BQ LUMINESCENCE NPN/PNP M12 40 TO 75mm |
| QL564 | 制造商:Aim & Thurlby Thandar Instruments 功能描述:PSU 56V 4A PECISION |
| QL564 SII | 制造商:Aim & Thurlby Thandar Instruments 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of Outputs:1, Output Voltage Min:0V, Output Voltage Max:56V, Output Current Min:0A, Output Current Max:4A, Power Rating:112W, Input Voltage:115VAC / 230VAC, RoHS Compliant: NA 制造商:TTI (THURLBY THANDAR INSTRUMENTS) 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of |
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