2
Preliminary
QL5432 - QuickPCI
TM
2
The QL5432 device in the QuickLogic QuickPCI ESP
(Embedded Standard Product) family provides a
complete and customizable PCI interface solution
combined with programmable logic. This device
eliminates any need for the designer to worry about
PCI bus compliance, yet allows for the maximum 32-
bit PCI bus bandwidth (132 MB/s).
The programmable logic portion of the device
contains 1427 QuickLogic Logic Cells, and 20
QuickLogic Dual-Port RAM Blocks. These
configurable RAM blocks can be configured in many
width/depth combinations. They can also be
combined with logic cells to form FIFOs, or be
initialized via Serial EEPROM on power-up and used
as ROMs.
The QL5432 device meets PCI 2.2 electrical and
timing specifications and has been fully hardware-
tested. This device also supports the Win'98 and
PC'98 standards. The QL5432 device features 3.3-
volt operation with multi-volt compatible I/Os. Thus it
can easily operate in 3-volt systems and is fully
compatible with 3.3V, 5V or Universal PCI card
applications.
The PCI Controller is a 32-bit/33 MHz PCI 2.2 Com-
pliant Master/Target Controller. It is capable of infi-
nite length Master Write and Read transactions at zero
wait states (132 MBytes/second). The Master will
never insert wait states during transfers, so data should
be supplied or received by FIFOs, which can be config-
ured in the programmable region of the device. The
Master is capable of initiating any type of PCI com-
mand, including configuration cycles and Memory
Write and Invalidate (MWI). This enables the QL5432
device to act as a PCI host. The Master Controller will
most often be operated by a DMA Controller in the
programmable region of the device. A DMA Control-
ler reference design is available.
The Target interface offers full PCI Configuration
Space and flexible target addressing. It supports zero-
wait-state target write and one-wait-state target read
operations. It also supports retry, disconnect with/
without data transfer, and target abort requested by
the backend. Any number of 32-bit BARs may be con-
figured, as either memory or I/O space. All required
and optional PCI 2.2 Configuration Space registers
can be implemented within the programmable region
of the device. A reference design of a Target Configu-
ration and Addressing module is provided.
The interface ports are divided into a set of ports for
master transactions and a set for target transactions.
The Master DMA controller and Target Configuration
Space and Address Decoding are done in the pro-
grammable logic region of the device. Since these
functions are not timing critical, leaving these ele-
ments in the programmable region allows the greatest
degree of flexibility to the designer. Reference DMA
controller, Configuration Space, and Address Decod-
ing blocks are included so that the design cycle can be
minimized.
The configuration space is completely customizable in
the programmable region of the device.
PCI address and command decoding is performed by
logic in the programmable section of the device. This
allows support for any size of memory or I/O space
for back-end logic. It also allows the user to implement
any subset of the PCI commands supported by the
QL5432. QuickLogic provides a reference Address
Register/Counter and Command Decode block.
Architecture Overview
PCI Controller
Configuration Space and
Address Decode