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参数资料
| 型号： | QL5432-33APQ208I |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 12/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APQ208I |
12
Preliminary
QL5432 - QuickPCI
TM
12
RAM Cell Synchronous Read Timing
RAM Cell Asynchronous Read Timing
Input-Only Cells
Clock Cells
Notes:
[6] The array distributed networks consist of 40 half columns and the global distributed networks consist of 44
half columns, each driven by an independent buffer. The number of half columns used does not affect clock
buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half
column.
Symbol
Parameter
Propagation Delays (ns)
Fanout
2
1.0
1.0
0.0
0.0
1.0
1.0
0.0
0.0
4.3
4.6
1
3
4
8
TSRA
THRA
TSRE
THRE
TRCRD
RA Setup Time to RCLK
RA Hold Time to RCLK
RE Setup Time to RCLK
RE Hold Time to RCLK
RCLK to RD [5]
1.0
0.0
1.0
0.0
4.0
1.0
0.0
1.0
0.0
4.9
1.0
0.0
1.0
0.0
6.1
Symbol
Parameter
Propagation Delays (ns)
Fanout
2
3.3
3.6
1
3
4
8
RPDRD
RA to RD [5]
3.0
3.9
5.1
Symbol
Parameter
Propagation Delays (ns)
Fanout
[5]
2
3
1.6
1.8
1.9
1.7
1.9
2.0
3.1
3.1
3.1
0.0
0.0
0.0
0.8
1.0
1.1
0.7
0.9
1.0
2.3
2.3
2.3
0.0
0.0
0.0
1
4
8
12
2.9
3.0
3.1
0.0
2.1
2.0
2.3
0.0
24
4.4
4.5
3.1
0.0
3.6
3.5
2.3
0.0
TIN
TINI
TISU
TIH
TlCLK
TlRST
TlESU
TlEH
High Drive Input Delay
High Drive Input, Inverting Delay
Input Register Set-Up Time
Input Register Hold Time
Input Register Clock To Q
Input Register Reset Delay
Input Register Clock Enable Setup Time
Input Register Clock Enable Hold Time
1.5
1.6
3.1
0.0
0.7
0.6
2.3
0.0
2.4
2.5
3.1
0.0
1.6
1.5
2.3
0.0
Propagation Delays (ns)
Loads per Half Column [6]
3
4
1.3
1.3
0.7
0.7
0.9
0.9
Symbols
Parameter
1
1.2
0.7
0.8
2
1.2
0.7
0.8
8
1.5
0.7
1.1
10
1.6
0.7
1.2
12
1.7
0.7
1.3
15
1.8
0.7
1.4
tACK
tGCKP
tGCKB
Array Clock Delay
Global Clock Pin Delay
Global Clock Buffer Delay
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