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参数资料
| 型号： | QL5432-33APQ208I |
| 英文描述： | ASIC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 5/20页 |
| 文件大小： | 559K |
| 代理商： | QL5432-33APQ208I |
5
QL5432 - QuickPCI
TM
The internal signals used to interface with the PCI controller in the QL5432 are listed below, along with a description
of each signal. The direction of the signal indicates if it is an input provided by the local interface (i) or an output pro-
vided by the PCI controller (o). Signals that end with the character ‘N’ should be considered active-low (for example,
Mst_IRDYN
).
PCI_Cmd[3:0]
I
PCI command to be used for the master transaction. This signal must remain unchanged throughout the period
when Mst_Burst_Req is active. PCI commands considered as reads include Interrupt Acknowledge, I/O Read,
Memory Read, Configuration Read, Memory Read Multiple, Memory Read Line. PCI commands considered as
writes include Special Cycle, I/O Write, Memory Write, Configuration Write, Memory Write and Invalidate.
Users should make sure that only valid PCI commands are supplied.
Request use of the PCI bus. When it is active, the core requests the PCI bus and then generates a master trans-
action. This signal should be held active until all requested data are transferred on the PCI bus and deactivated
in the 2nd clock cycle following the last data transfer on PCI (to avoid being considered as requesting a new
transaction).
Address for master DMA writes. This address must be treated as valid from the beginning of a DMA write until
the DMA write operation is complete. It should be incremented (by 4 bytes) each time data is transferred on
the PCI bus.
Address for master DMA reads. This address must be treated as valid from the beginning of a DMA read until
the DMA read operation is complete. It should be incremented (by 4 bytes) each time data is transferred on the
PCI bus.
Data for master DMA writes (to PCI bus).
Byte enables for master DMA reads and writes. Active-low.
Data and byte enable valid on Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both master read
and write).
Data receive acknowledge for Mst_WrData[31:0] (for master write only) and Mst_BE[3:0] (for both). This
serves as the PUSH control for the internal FIFO and the POP control for the external FIFO (in FPGA region)
which provides data and byte enables to the PCI32 core.
Byte enable select for master transactions. When low, Mst_BE[3:0] should remain constant throughout the
entire transfer (when Mst_Burst_Req is active) and it is used for every data phase of the master transaction.
When high, Mst_BE[3:0] pushed into internal FIFO (along with data in case of master write) is used. Should be
held constant throughout the transaction.
Master write transaction is completed. Active for only one clock cycle.
Master read termination mode select when Mst_BE_Sel is high. When both Mst_BE_Sel and
Mst_Rd_Term_Sel are high, master read termination happens when the internal FIFO is empty, and
Mst_Two_Reads and Mst_One_Read are ignored. When either signal is low, Mst_Two_Reads and
Mst_One_Read are used to signal end of master read. Should be held constant throughout the transaction.
This signals to the PCI32 core that only one data transfer remains to be read in the burst read.
Two data transfers remain to be read in the burst read. It is not used for single-data-phase master read
transactions.
Master read data valid on Usr_Addr_WrData[31:0]. This serves as the PUSH control for the external FIFO (in
FPGA region) that receives data from the PCI32 core.
Master read transaction is completed. Active for only one clock cycle.
Internal FIFO flush. FIFO flushed immediately after it is active (synchronized with PCI clock).
Enable Latency Counter. Set to 0 to ignore the Latency Timer in the PCI configuration space (offset 0Ch).
For full PCI compliance, this port should be always set to 1.
Data was transferred on the previous PCI clock. Useful for updating DMA transfer counts on DMA Read
operations.
Active during the last data transfer of a master transaction.
Copy of the PCI REQN signal generated by QL5x33 as PCI master. Not usually used in the back-end design.
Mst_Burst_Req
I
Mst_WrAd[31:0]
I
Mst_RdAd[31:0]
I
Mst_WrData[31:0]
Mst_BE[3:0]
Mst_WrData_Valid
I
I
I
Mst_WrData_Rdy
O
Mst_BE_Sel
I
Mst_WrBurst_Done
Mst_Rd_Term_Sel
O
I
Mst_One_Read
Mst_Two_Reads
I
I
Mst_RdData_Valid
O
Mst_RdBurst_Done
Flush_FIFO
Mst_LatCntEn
O
I
I
Mst_Xfer_D1
O
Mst_Last_Cycle
Mst_REQN
O
O
PCI Master Interface
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