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参数资料
| 型号： | QL5822-33APT280C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA280 |
| 封装： | 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MO-205, LFBGA-280 |
| 文件页数： | 4/76页 |
| 文件大小： | 1128K |
| 代理商： | QL5822-33APT280C |
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2007 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. L
12
Figure 5: Cascaded RAM Modules
The RAM modules are dual-port, with completely independent READ and WRITE ports and separate READ
and WRITE clocks. The READ ports support asynchronous and synchronous operation, while the WRITE
ports support synchronous operation. Each port has 18 data lines and 8 address lines, allowing word lengths
of up to 18 bits and address spaces of up to 256 words. Depending on the mode selected, however, some
higher order data or address lines may not be used.
The Write Enable (WE) line acts as a clock enable for synchronous write operation. The Read Enable (RE) acts
as a clock enable for synchronous READ operation (ASYNCRD input low), or as a flow-through enable for
asynchronous READ operation (ASYNCRD input high).
Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by
connecting corresponding address lines together and dividing the words between modules.
A similar technique can be used to create depths greater than 256 words. In this case address signals higher
than the MSB are encoded onto the write enable (WE) input for WRITE operations. The READ data outputs
are multiplexed together using encoded higher READ address bits for the multiplexer SELECT signals.
The RAM blocks can be loaded with data generated internally (typically for RAM or FIFO functions) or with
data from an external PROM (typically for ROM functions).
WDATA
RDATA
WADDR
WDATA
RADDR
RAM
Module
(2,304 bits)
RAM
Module
(2,304 bits)
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相关代理商/技术参数 |
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|---|---|
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