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参数资料
| 型号： | QL5822-33APT280C |
| 厂商： | QUICKLOGIC CORP |
| 元件分类： | 总线控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA280 |
| 封装： | 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, PLASTIC, MO-205, LFBGA-280 |
| 文件页数： | 75/76页 |
| 文件大小： | 1128K |
| 代理商： | QL5822-33APT280C |
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2007 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. L
8
PCI Internal Signals
Usr_MstWrAd_Sel
I
Used when a target read operation should return the value set on the Mst_WrAd[31:0]
pins. This select pin saves on logic which would otherwise need to be used to multiplex
Mst_WrAd[31:0] into the Usr_RdData[31:0] bus. When this signal is asserted, the data
on Usr_RdData[31:0] is ignored.
Cfg_PERR_Det
O
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status
Register must be set in the PCI configuration space (offset 04h).
Cfg_SERR_Sig
O
System error asserted on the PCI bus. When this signal is active, the Signalled System
Error bit, bit 14 of the Status Register, must be set in the PCI configuration space (offset
04h).
Cfg_MstPERR_Det
O
Data parity error detected on the PCI bus by the master. When this signal is active, bit
8 of the Status Register must be set in the PCI configuration space (offset 04h).
Usr_TRDY
O
Inverted copy of the TRDYN signal as driven by the PCI target interface. Valid only within
a target access.
Usr_STOPO
O
Inverted copy of the STOPN signal as driven by the PCI target interface. Valid only
within a target access.
Usr_DEVSEL
O
Inverted copy of the DEVSELN signal as driven by the PCI target interface. Valid only
within a target access.
Usr_Last_Cycle_D1
O
Active one clock cycle after the last data phase (may not with data transfer) occurs on
PCI and inactive one clock cycle afterwards.
Usr_Rdy
I
Used to delay (add wait states to) a target PCI transaction when the backend needs
additional time to provide data (read) or accept data (write). Subject to PCI latency
restrictions.
Usr_Stop
I
Used to prematurely stop a PCI target access on the next PCI clock.
Usr_Abort
I
Used to signal Target Abort on PCI when the backend has fatal errors and is unable to
complete a transaction. Rarely used.
Table 4: PCI Internal Signals
Signal
I/O
Description
PCI_clock
O
PCI clock.
PCI_reset
O
PCI reset signal.
PCI_IRDYN_D1
O
Copy of the IRDYN signal from the PCI bus, delayed by one clock.
PCI_FRAMEN_D1
O
Copy of the FRAMEN signal from the PCI bus, delayed by one clock.
PCI_DEVSELN_D1
O
Copy of the DEVSELN signal from the PCI bus, delayed by one clock.
PCI_TRDYN_D1
O
Copy of the TRDYN signal from the PCI bus, delayed by one clock.
PCI_STOPN_D1
O
Copy of the STOPN signal from the PCI bus, delayed by one clock.
PCI_IDSEL_D1
O
Copy of the IDSEL signal from the PCI bus, delayed by one clock.
Table 3: PCI Target Interface (Continued)
Signal
I/O
Description
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