参数资料
型号: QLX4300SIQSR
厂商: Intersil
文件页数: 2/21页
文件大小: 0K
描述: IC EQUALIZER REC 3.125GBPS 46QFN
标准包装: 100
系列: QLx™
应用: 数据传输
接口: SMBus(2 线/I²C)
电源电压: 1.1 V ~ 1.3 V
封装/外壳: 46-WFQFN 裸露焊盘
供应商设备封装: 46-TQFN
包装: 带卷 (TR)
安装类型: 表面贴装
10
FN6982.1
November 19, 2009
Operation
The QLx4300-S45 is an advanced quad lane-extender for
high-speed interconnects. A functional diagram of one of
the four channels in the QLx4300-S45 is shown in
Figure 17. In addition to a robust equalization filter to
compensate for channel loss and restore signal fidelity,
the QLx4300-S45 contains unique integrated features to
preserve special signaling protocols typically broken by
other equalizers. The signal detect function is used to
mute the channel output when the equalized signal falls
below the level determined by the Detection Threshold
(DT) pin voltage. This function is intended to preserve
periods of line silence (“quiescent state” in InfiniBand
contexts).
As illustrated in Figure 17, the core of each high-speed
signal path in the QLx4300-S45 is a sophisticated
equalizer followed by a limiting amplifier. The equalizer
compensates for skin loss, dielectric loss, and impedance
discontinuities in the transmission channel. Each
equalizer is followed by a limiting amplification stage that
provides a clean output signal with full amplitude swing
and fast rise-fall times for reliable signal decoding in a
subsequent receiver.
Individually Adjustable Equalization Boost
Each channel in the QLx4300-S45 features an
independently settable equalizer for custom signal
restoration. Each equalizer can be set to one of 32 levels
of compensation when the serial bus is used to program
FIGURE 13. INPUT DIFFERENTIAL RETURN LOSS
FIGURE 14. OUTPUT DIFFERENTIAL RETURN LOSS
FIGURE 15. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNEL
FIGURE 16. DIFFERENTIAL CROSSTALK BETWEEN
ADJACENT INPUT CHANNELS
Typical Performance Characteristics (Continued)
-35
-30
-25
-20
-15
-10
-5
0
00.5
11.522.533.5
4
Frequency (GHz)
SDD
1
(
d
B)
Channel 1
Channel 2
Channel 3
Channel 4
-35
-30
-25
-20
-15
-10
-5
0
00.5
11.522.533.5
4
Frequency (GHz)
S
D
D2
2
(
d
B)
Channel 1
Channel 2
Channel 3
Channel 4
FIGURE 17. FUNCTIONAL DIAGRAM OF A SINGLE
CHANNEL WITHIN THE QLx4300-S45
+
-
SETTABLE
EQUILIZER
LIMITING
AMPLIFIER
AMPLITUDE
DETECTOR
MUTE
ENABLED
OUT[k]
IN[k]
IS[k]
>200k
Ω
BIT SELECT
(CP[k]/DI)
DT
QLx4300-S45
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