参数资料
| 型号： | QLX4300SIQSR |
| 厂商： | Intersil |
| 文件页数： | 6/21页 |
| 文件大小： | 0K |
| 描述： | IC EQUALIZER REC 3.125GBPS 46QFN |
| 标准包装： | 100 |
| 系列： | QLx™ |
| 应用： | 数据传输 |
| 接口： | SMBus（2 线/I²C） |
| 电源电压： | 1.1 V ~ 1.3 V |
| 封装/外壳： | 46-WFQFN 裸露焊盘 |
| 供应商设备封装： | 46-TQFN |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
14
FN6982.1
November 19, 2009
Optimal Cable Boost Settings
The settable equalizing filter within the QLx4300-S45
enables the device to optimally compensate for
frequency-dependent attenuation across a wide variety
of channels, data rates, and encoding schemes. For the
optimal boost setting when transmitting a PRBS-7 signal.
The optimal boost setting is defined as the equalizing
filter setting that minimizes the output residual jitter of
the QLx4300-S45. The settings in Table 4 represent the
optimal settings for the QLx4300-S45 across an ambient
temperature range of 0°C to +70°C. The optimal setting
at room temperature (+20°C to +40°C) is generally one
to two settings lower than the values listed in Table 3.
Register Description
The QLx4300-S45’s internal registers are listed in
Table 4. Register 1 determines whether the CP pins or
register values 2 through 21 are used to set the boost
level. When this register is set, the QLx4300-S45 uses
registers 2-6, 7-11, 12-16, and 17-21 to set the boost
level of equalizers 1, 2, 3, and 4. When register 1 is not
set, the CP pins are used to determine the boost level for
each equalizer channel. The use of five registers for each
equalizer channel allows all 32 boost levels as candidate
boost levels.
TABLE 3. OPTIMAL CABLE BOOST SETTINGS
CABLE
APPROX. LOSS @
1.5625GHz (dB)
QLx4300-S45
BOOST
Cable A
17
12
Cable B
23
16
Cable C
28
23
NOTE: Optimal boost settings should be determined on an
application-by-application basis to account for variations in
channel type, loss characteristics, and encoding schemes. The
settings in this table are presented as guidelines to be used as
a starting point for application-specific optimization.
TABLE 4. DESCRIPTION OF INTERNAL SERIAL REGISTERS
REGISTER
EQUALIZER
CHANNEL
DESCRIPTION
1
1-4
CP control override – Use registers 2 through 21 (rather than CP pins) to establish the boost
levels when this bit is set.
2
1
Equalizer setting bit 0 (LSB).
3
Equalizer setting bit 1.
4
Equalizer setting bit 2.
5
Equalizer setting bit 3.
6
Equalizer setting bit 4 (MSB).
7
2
Equalizer setting bit 0 (LSB).
8
Equalizer setting bit 1.
9
Equalizer setting bit 2.
10
Equalizer setting bit 3.
11
Equalizer setting bit 4 (MSB).
12
3
Equalizer setting bit 0 (LSB).
13
Equalizer setting bit 1.
14
Equalizer setting bit 2.
15
Equalizer setting bit 3.
16
Equalizer setting bit 4 (MSB).
17
4
Equalizer setting bit 0 (LSB).
18
Equalizer setting bit 1.
19
Equalizer setting bit 2.
20
Equalizer setting bit 3.
21
Equalizer setting bit 4 (MSB).
QLx4300-S45
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| QLX4600LIQSR | 功能描述:接口 - 专用 6 GBS QD CH LANE EXTENDER RoHS:否 制造商:Texas Instruments 产品类型:1080p60 Image Sensor Receiver 工作电源电压:1.8 V 电源电流:89 mA 最大功率耗散: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:BGA-59 |
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