参数资料
型号: QS5917T-100TJ
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: Clock Driver
英文描述: 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28
封装: PLASTIC, LCC-28
文件页数: 3/7页
文件大小: 75K
代理商: QS5917T-100TJ
INDUSTRIALTEMPERATURERANGE
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
3
Pin Names
I/O
Description
SYNC0
I
Reference clock input
SYNC1
I
Referenceclockinput
REF_SEL
I
Reference clock select. When 1, selects SYNC1. When 0, selects SYNC0.
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
FEEDBACK
I
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output frequency
relationships.SeetheFrequencySelectionTableformoreinformation.
Q0 -Q4
O
Clockoutputs
Q5
O
Clock output. Matched in frequency, but inverted with respect to Q.
2xQ
O
Clock output. Matched in phase, but frequency is double the Q frequency.
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
LOCK
O
PLLlockindicationsignal.1indicatespositivelock.0indicatesthatthePLLisnotlockedandoutputsmaynotbesynchronizedtotheinputs.
RST
I
Asynchronousreset.Resetsalloutputregisters.When0,alloutputsareheldinatri-statedcondition.When1,outputsareenabled(normal
operation).
PLL_EN
I
PLL enable. When 1, PLL is enabled (normal operation). When 0, PLL is disabled (for testing purposes).
N C
No Connection
PIN DESCRIPTION
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
Description
– 70
–100
–132
Units
F2XQ
Max Frequency, 2xQ output
70
100
132
MHz
FQ
Max Frequency, Q0 - Q4, Q5 outputs
35
50
66
MHz
FQ/2
Max Frequency, Q/2 output
17.5
25
33
MHz
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