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参数资料
| 型号： | QS5917T-100TJ |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | Clock Driver |
| 英文描述： | 5917 SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封装： | PLASTIC, LCC-28 |
| 文件页数： | 4/7页 |
| 文件大小： | 75K |
| 代理商： | QS5917T-100TJ |
INDUSTRIALTEMPERATURERANGE
4
QS5917T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
(allowable range)
Output Frequency Relationships
FREQ_SEL
Feedback
Min.
Max
Q/2
Q5
Q Outputs
2XQ
1
Q/2
14
F2XQ
/ 4
SYNC
– SYNC X 2
SYNC X 2
SYNC X 4
1Q0 -Q4
28
F2XQ
/ 2
SYNC / 2
– SYNC
SYNC
SYNC X 2
1Q5
28
F2XQ
/ 2
– SYNC / 2
SYNC
– SYNC
– SYNC X 2
1
2xQ
56
F2XQ(1)
SYNC / 4
– SYNC / 2
SYNC / 2
SYNC
0
Q/2
7
F2XQ
/ 8
SYNC
– SYNC X 2
SYNC X 2
SYNC X 4
0Q0 -Q4
14
F2XQ
/ 4
SYNC / 2
– SYNC
SYNC
SYNC X 2
0Q5
14
F2XQ
/ 4
– SYNC / 2
SYNC
– SYNC
– SYNC X 2
0
2xQ
28
F2XQ
/ 2
SYNC / 4
– SYNC / 2
SYNC / 2
SYNC
NOTE:
1. For the –132 speed grade, maximum input frequency is restricted to 100MHz.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage Level
Guaranteed Logic HIGH level
2
—
V
VIL
Input LOW Voltage Level
Guaranteed Logic LOW level
—
0.9
V
VOH
Output HIGH Voltage
VDD = Min., IOH =
24mA (1)
2.4
—
V
VDD = Min., IOH =
100μA3
—
VOL
OutputLOWVoltage
VDD = Min., IOL = 24mA (1)
—
0.55
V
VDD = Min., IOL = 100
μA
—
0.2
IOZ
OutputLeakageCurrent
VOUT = VDD or GND, VDD = Max.
—
±5
μA
IIN
InputLeakageCurrent
VIN = AVDD or GND, AVDD = Max.
—
±5
μA
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
NOTE:
1. IOL and IOH are 12mA and –12mA, respectively, for the LOCK output.
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions(1)
Typ.
Max.
Unit
ΔICC
Input Power Supply Current per TTL Input HIGH (2)
VDD = Max., VIN = 3.4V
0.4
1.5
mA
ICCD
Dynamic Power Supply Current
VDD = Max
—
0.4
mA/MHz
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. This specification does not apply to the PLL_EN input.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| QS5917T-100TJ8 | 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER PLCC28 - Tape and Reel |
| QS5917T-100TJG | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK DRVR SGL 28PLCC - Rail/Tube |
| QS5917T-100TJG8 | 制造商:Integrated Device Technology Inc 功能描述:CLK DRVR PLL, FILTER. PLCC28 - Tape and Reel |
| QS5917T100TQ | 制造商:Integrated Device Technology Inc 功能描述: |
| QS5917T-100TQ | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER |
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