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参数资料
| 型号： | QS5930-50TQ |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | Clock Driver |
| 英文描述： | 5930 SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封装： | QSOP-20 |
| 文件页数： | 3/6页 |
| 文件大小： | 67K |
| 代理商： | QS5930-50TQ |
3
INDUSTRIALTEMPERATURERANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to FMAX_Q x2. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output
frequencies.
FREQUENCY SELECTION TABLE
Output Used for
SYNC (MHz)
(allowable range) (1)
Output Frequency Relationships
FREQ_SEL
Feedback
Min.
Max
Q/2
Q0 - Q4
HIGH
Q/2
14
FMAX _Q/2
SYNC
SYNC X 2
HIGH
Q0 -Q4
28
FMAX _Q
SYNC / 2
SYNC
LOW
Q/2
7
FMAX _Q/2 /2
SYNC
SYNC X 2
LOW
Q0 -Q4
14
FMAX _Q /2
SYNC / 2
SYNC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: TA = –40°C to +85°C, AVDD/VDD = 5V ± 5%
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2
—
V
VIL
Input LOW Voltage
Guaranteed Logic LOW Level
—
0.8
V
VOH
Output HIGH Voltage
IOH =
24mA
2.4
—
V
IOH =
100μA
3—
—
V
VOL
Output LOW Voltage
VDD = Min., IOL = 24mA
—
0.55
V
VDD = Min., IOL = 100
μA
——
0.2
V
IOZ
Output Leakage Current
VOUT = VDD or GND,
VDD = Max., Outputs Disabled
——
5
μA
IIN
Input Leakage Current
AVDD = Max., VIN = AVDD or GND
—
5
μA
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
IDDQ
Quiescent Power Supply Current
VDD = Max., OE/
RST = LOW,
SYNC = LOW, All outputs unloaded
—1
mA
ΔIDD
Power Supply Current per Input HIGH
VDD = Max., VIN = 3V
1
30
μA
IDDD
Dynamic Power Supply Current
VDD = Max., CL = 0pF
0.2
0.3
mA/MHz
INPUT TIMING REQUIREMENTS
Symbol
Description (1)
Min.
Max.
Unit
tR, tF
Maximum input rise and fall times, 0.8V to 2V
—
3
ns
FI
Input Clock Frequency, SYNC (1)
7FMAX _Q
MHz
tPWC
Input clock pulse, HIGH or LOW (2)
2—
ns
DH
Duty Cycle, SYNC (2)
25
75
%
NOTES:
1.
See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2.
Where pulse witdh implied by DH is less than tWPC limit, tWPC limit applies
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