参数资料
| 型号： | QT60240-ISG QS130 |
| 厂商： | Atmel |
| 文件页数： | 12/26页 |
| 文件大小： | 0K |
| 描述： | SENSOR IC MTRX TOUCH24KEY 32-QFN |
| 标准包装： | 1 |
| 系列： | QMatrix™ |
| 类型： | 电容性 |
| 输入数/键： | 24 键 |
| 分辨率（位）： | 10 b |
| 评估套件： | 可供 |
| 数据接口： | I²C，串行，SPI? |
| 电压基准： | 外部 |
| 电源电压： | 1.8V，3.3V，5V |
| 电流 - 电源： | 4.6mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | 427-1126-1 |
13
4.7 Setups
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4.6 Cal All
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4.5 Raw Data Commands
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4.4 Report Detections for All Keys
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4.3 Reading Data From the Device
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4.2 Writing Data to the Device
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4.1 Introduction
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4 Control Commands
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3.4 CHANGE Pin
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3.3 I2C Port
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3.2 Shift Register Output Mode
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3.1 Introduction
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3 Interfaces
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2.16 Wiring
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2.15 Sleep
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2.14 Detection Integrators
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2.13 Spread Spectrum Acquisitions
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2.12 Reset Input
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2.11 Startup / Calibration Times
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2.10 Power Supply Considerations
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2.9.3 PCB Cleanliness
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2.9.2 LED Traces and Other Switching Signals
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2.9.1 Overview
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2.9 PCB Layout, Construction
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2.8 Key Design
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2.7 Matrix Series Resistors
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2.6 Signal Levels
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2.5 Sample Resistors
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2.4 Sample Capacitor Saturation
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2.3 Cs Sample Capacitor Operation
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2.2 Burst Paring
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2.1 Matrix Scan Sequence
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2 Hardware and Functional
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1.3 Enabling / Disabling Keys
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1.2 Part Differences
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1.1 Introduction
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3
1 Overview
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7.8 Moisture Sensitivity Level (MSL)
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7.7 Marking
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7.6 Mechanical Dimensions
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7.5 Power Consumption
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7.4 Timing Specifications
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7.3 DC Specifications
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7.2 Recommended Operating Conditions
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7.1 Absolute Maximum Electrical Specifications
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7 Specifications
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6.16 Setups Block
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6.15 Drift Hold Time - DHT
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6.14 Awake Timeout - AWAKE
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6.13 Wake on Key Touch - WAKE
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6.12 Sleep Duration - SLEEP
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6.11 Mains Sync - MSYNC
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6.10 Oscilloscope Sync - SSYNC
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6.9 Adjacent Key Suppression - AKS
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6.8 Burst Length - BL
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6.7 Positive Recalibration Delay - PRD
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6.6 Negative Recal Delay - NRD
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6.5 Detect Integrators - NDIL, FDIL
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6.4 Drift Compensation - NDRIFT, PDRIFT
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6.3 Positive Threshold - PTHR
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6.2 Negative Threshold - NTHR
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6.1 Introduction
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6 Setups
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5.6 Combining Address and Data Packets Into a Transmission
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5.5 Data Packet Format
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5.4 Address Packet Format
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5.3 START and STOP Conditions
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5.2 Transferring Data Bits
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5.1 Interface Bus
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5 I2C Operation
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lQ
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QT60240-ISG R8.06/0906
Contents
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