参数资料
型号: R1EX25064ATA00A#S0
厂商: Renesas Electronics America
文件页数: 10/24页
文件大小: 0K
描述: IC EEPROM 64K 5MHZ 8TSSOP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 3MHz,5MHz
接口: SPI 串行
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 8-TSSOP
包装: 标准包装
其它名称: R1EX25064ATA00A#S0DKR
R1EX25032Axx00A/R1EX25064Axx00A
Pin Function
Serial data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of serial
clock (C).
Serial data input (D)
This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be
written. Values are latched on the rising edge of serial clock (C).
Serial clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data present at serial data input
(D) are latched on the rising edge of serial clock (C). Data on serial data output (Q) changes after the falling edge of
serial clock (C).
Chip select ( S )
When this input signal is high, the device is deselected and serial data output (Q) is at high impedance. Unless an
internal write cycle is in progress, the device will be in the standby mode. Driving chip select ( S ) low enables the
device, placing it in the active power mode. After power-up, a falling edge on chip select ( S ) is required prior to the
start of any instruction.
Hold ( HOLD )
The hold ( HOLD ) signal is used to pause any serial communications with the device without deselecting the device.
During the hold condition, the serial data output (Q) is high impedance, and serial data input (D) and serial clock (C)
are don’t care. To start the hold condition, the device must be selected, with chip select ( S ) driven low.
Write protect ( W )
The main purpose of this input signal is to freeze the size of the area of memory that is protected against write
instructions (as specified by the values in the BP1 and BP0 bits of the status register). This pin must be driven either
high or low, and must be stable during all write operations.
REJ03C0358-0002.Rev.0.02 Jan.14.2009
page 8 of 20
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