参数资料
型号: R1RW0416DGE-2LR
厂商: Renesas Technology Corp.
元件分类: DRAM
英文描述: 4M High Speed SRAM (256-kword x 16-bit)
中文描述: 4分高速SRAM(256 - KWord的x 16位)
文件页数: 8/16页
文件大小: 100K
代理商: R1RW0416DGE-2LR
R1RW0416D Series
Rev.1.00, Mar.12.2004, page 8 of 14
Write Cycle
R1RW0416D
-2
Parameter
Symbol
Min
Max
Unit
Notes
Write cycle time
t
WC
t
AW
t
CW
t
WP
t
BW
t
AS
t
WR
t
DW
t
DH
t
OW
t
OHZ
t
WHZ
12
6
ns
Address valid to end of write
8
ns
Chip select to end of write
8
ns
8
Write pulse width
8
ns
7
Byte select to end of write
8
ns
Address setup time
0
ns
5
Write recovery time
0
ns
6
Data to write time overlap
6
ns
Data hold from write time
0
ns
Write disable to output in low-Z
3
ns
1
Output disable to output in high-Z
ns
1
Write enable to output in high-Z
Notes: 1. Transition is measured
±
200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or
after the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. t
is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. t
is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (t
). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. t
CW
is measured from the later of CS# going low to the end of write.
6
ns
1
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