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参数资料
| 型号： | R2051K02 |
| 厂商： | RICOH COMPANY LTD |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, QCC12 |
| 封装： | 2 X 2 MM, 0.85 MM PITCH, ULTRA-COMPACT, FFP, 12 PIN |
| 文件页数： | 17/53页 |
| 文件大小： | 343K |
| 代理商： | R2051K02 |
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R2051 Series
12345
Rev.1.04
- 24 -
receiving side. When transmission of 1byte data next to preceding 1byte of data is received the receiving side
releases the SDA pin at falling edge of the SCL 9bit of clock pulses or when the receiving side switches to the
transmission side it starts data transmission. When the master is receiving side, it generates no acknowledge
signal after last 1byte of data from the slave to tell the transmitter that data transmission has completed. The slave
side (transmission side) continues to release the SDA pin so that the master will be able to generate Stop
Condition, after falling edge of the SCL 9bit of clock pulses.
SCL
from the master
SDA from
the transmission side
SDA from
the receiving side
1
2
8
9
Acknowledge
signal
Start
Condition
(3) Data Transmission Format in I
2C-Bus
I
2C-Bus has no chip enable signal line. In place of it, each device has a 7bit Slave Address allocated. The first
1byte is allocated to this 7bit address and to the command (R/W) for which data transmission direction is
designated by the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and
after bytes are read, when 8bit is “H” and when write “L”.
The Slave Address of the R2051 is specified at (0110010).
At the end of data transmission / receiving, Stop Condition is generated to complete transmission. However, if start
condition is generated without generating Stop Condition, Repeated Start Condition is met and transmission /
receiving data may be continue by setting the Slave Address again. Use this procedure when the transmission
direction needs to be change during one transmission.
S
A
Data
/A P
Data is written to the slave
from the master
S
0
A
Slave Address
Data
A
A P
When data is read from the
slave immediately after 7bit
addressing from the master
Master to slave
Slave to master
Sr Repeated Start Condition
P
Stop Condition
A
/A Acknowledge Signal
R/W=1(Read)
(0110010)
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Data
R/W=0(Write)
(0110010)
When
the
transmission
direction is to be changed
during transmission.
Sr
1
0
A
R/W=0(Write)
A
Data
R/W=1(Read)
(0110010)
S
1
A
/A P
Inform read has been completed by not generate
an acknowledge signal to the slave side.
Data
S
Start Condition
(0110010)
Slave Address
Salve Address
Slave Address
Data
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PDF描述 |
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| R3F10011NSP | FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| R2051K02-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2051S01-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2051S02-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2051S03-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
| R2051T01-E2 | 制造商:RICOH 制造商全称:RICOH electronics devices division 功能描述:2 wire interface Real-Time Clock ICs with Battery Backup switch-over Function |
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