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| 型号： | R5F3650KNFA |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | MICROCONTROLLER, PQFP100 |
| 封装： | 20 X 14 MM, 0.65 MM PITCH, QFP-100 |
| 文件页数： | 15/81页 |
| 文件大小： | 879K |
| 代理商： | R5F3650KNFA |
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113
4317K–AVR–03/2013
AT90PWM2/3/2B/3B
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGMn3:0) bits and Compare Output mode (COMnx1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See “16-bit Timer/Counter1 with PWM” on page 104.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 15-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = n for Timer/Counter n), and the “x” indicates Output
Compare unit (x). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 15-4. Output Compare Unit, Block Diagram
The OCRnx Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCRnx Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-
put glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-
abled the CPU will access the OCRnx directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCRnx Registers must be done via the TEMP Reg-
ister since the compare of all 16 bits is done continuously. The high byte (OCRnxH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
OCFnx (Int.Req.)
= (16-bit Comparator )
OCRnx Buffer (16-bit Register)
OCRnxH Buf. (8-bit)
OCnx
TEMP (8-bit)
DATA BUS (8-bit)
OCRnxL Buf. (8-bit)
TCNTn (16-bit Counter)
TCNTnH (8-bit)
TCNTnL (8-bit)
COMnx1:0
WGMn3:0
OCRnx (16-bit Register)
OCRnxH (8-bit)
OCRnxL (8-bit)
Waveform Generator
TOP
BOTTOM
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相关代理商/技术参数 |
参数描述 |
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| R5F3650KNFB | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:This MCU consumes low power, and supports operating modes |
| R5F3650KNFB#U0 | 功能描述:MCU 4KB FLASH 384/16K 100-LQFP RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:M16C™ M16C/60/65 标准包装:96 系列:PIC® 16F 核心处理器:PIC 芯体尺寸:8-位 速度:20MHz 连通性:I²C，SPI 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:11 程序存储器容量:3.5KB（2K x 14） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:128 x 8 电压 - 电源 (Vcc/Vdd):2.3 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 包装:管件 |
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| R5F3650MCDFB | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:televisions, household appliances, office equipment, communication devices |
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