参数资料
型号: R5F56108VNFP
元件分类: 微控制器/微处理器
英文描述: 64-BIT, FLASH, MICROCONTROLLER, PQFP144
封装: 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件页数: 23/85页
文件大小: 1355K
代理商: R5F56108VNFP
RX610 Group
1. Overview
R01DS0097EJ0100
Rev.1.00
Page 3 of 83
Apr 22, 2011
Classification
Module/Function
Description
Interrupt
Interrupt control unit
Peripheral function interrupts: 116
External interrupts: 16 (pins IRQ15 to IRQ0)
Non-maskable interrupt: 1 (the NMI pin)
Eight priority orders specifiable
External bus extension
The external address space can be divided into eight areas (CS0 to CS7), each of
which is independently controllable.
Capacity of each area: 16 Mbytes
Chip-select signals (CS0# to CS7#) can be output for each area.
8-bit or 16-bit bus space can be specified for each area.
The data arrangement is selectable as little endian or big endian for each area. (only
for data)
Separate bus system
Wait control
Write buffer programming
DMA controller
4-channel DMA transfer available
Activation sources: Software trigger, external interrupts, and interrupt requests from
peripheral functions
DMA
Data transfer controller
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activated by interrupt requests (chain transfer enabled)
I/O ports
Programmable I/O ports
I/O pins: 117 (144-pin LQFP), 140 (176-pin LFBGA)
Pull-up resistors: 40
Open-drain outputs: 16
5-V tolerance: 10
16-bit timer pulse unit
(16 bits x 6 channels) x 2 units
Up to 16 pulse inputs and outputs
Select from among 7 or 8 counter-input clocks for each channel
Input capture/output compare function
Maximum of 15-phase PWM output possible in PWM mode
Buffered operation, phase counting mode (two-phase encoder input), and cascaded
operation (32 bits x 2 channels) settable for each channel
PPG output trigger can be generated
Conversion start trigger for the A/D converter can be generated
Programmable pulse
generator
(4 bits x 4 groups) x 2 units
Provides pulse outputs by using the TPU output as a trigger
Maximum of 32-bit pulse output possible
8-bit timer
(8 bits x 2 channels) x 2 units
Select from among 8 clock sources (7 internal clocks and 1 external clock)
Allows the output of pulse trains with a desired duty cycle or PWM signals
Cascading of 2 channels enables it to be used as a 16-bit timer
Generation of trigger to start A/D converter conversion
Capable of generating baud rate clock for SCI5 and SCI6
Timer
Compare match timer
(16 bits x 2 channels) x 2 units
Select from among 4 counter-input clocks
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相关代理商/技术参数
参数描述
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