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参数资料
型号： R5F56108VNFP
元件分类： 微控制器/微处理器
英文描述： 64-BIT, FLASH, MICROCONTROLLER, PQFP144
封装： 20 X 20 MM, 0.50 MM PITCH, PLASTIC, LQFP-144
文件页数： 50/85页
文件大小： 1355K
代理商： R5F56108VNFP
RX610 Group
4. I/O Registers
R01DS0097EJ0100
Rev.1.00
Page 54 of 83
Apr 22, 2011
Address
Module
Abbreviation
Register Name
Register
Abbreviation
Number
of Bits
Access
Size
Number of
Access
Cycles
0008 C32Ch
ICU
IRQ control register 12
IRQCR12
8
2 to 3 PCLK
*7
0008 C32Dh
ICU
IRQ control register 13
IRQCR13
8
2 to 3 PCLK
*7
0008 C32Eh
ICU
IRQ control register 14
IRQCR14
8
2 to 3 PCLK
*7
0008 C32Fh
ICU
IRQ control register 15
IRQCR15
8
2 to 3 PCLK
*7
0008 C340h
ICU
Software standby release IRQ enable register
SSIER
16
2 to 3 PCLK
*7
0008 C350h
ICU
Non-maskable interrupt enable register
NMIER
8
2 to 3 PCLK
*7
0008 C351h
ICU
NMI pin interrupt control register
NMICR
8
2 to 3 PCLK
*7
0008 C352h
ICU
Non-maskable interrupt status register
NMISR
8
2 to 3 PCLK
*7
0008 C353h
ICU
Non-maskable interrupt clear register
NMICLR
8
2 to 3 PCLK
*7
007F C402h
FLASH
Flash mode register
FMODR
8
2 to 3 PCLK
*7
007F C410h
FLASH
Flash access status register
FASTAT
8
2 to 3 PCLK
*7
007F C411h
FLASH
Flash access error interrupt enable register
FAEINT
8
2 to 3 PCLK
*7
007F C412h
FLASH
Flash ready interrupt enable register
FRDYIE
8
2 to 3 PCLK
*7
007F C440h
FLASH
Data flash read enable register
DFLRE
16
2 to 3 PCLK
*7
007F C450h
FLASH
Data flash programming/erasure enable register
DFLWE
16
2 to 3 PCLK
*7
007F C454h
FLASH
FCU RAM enable register
FCURAME
16
2 to 3 PCLK
*7
007F FFB0h
FLASH
Flash status register 0
FSTATR0
8
2 to 3 PCLK
*7
007F FFB1h
FLASH
Flash status register 1
FSTATR1
8
2 to 3 PCLK
*7
007F FFB2h
FLASH
Flash P/E mode entry register
FENTRYR
16
2 to 3 PCLK
*7
007F FFB4h
FLASH
Flash protection register
FPROTR
16
2 to 3 PCLK
*7
007F FFB6h
FLASH
Flash reset register
FRESETR
16
2 to 3 PCLK
*7
007F FFBAh
FLASH
FCU command register
FCMDR
16
2 to 3 PCLK
*7
007F FFC8h
FLASH
FCU processing switching register
FCPSR
16
2 to 3 PCLK
*7
007F FFCAh
FLASH
Data flash blank check control register
DFLBCCNT
16
2 to 3 PCLK
*7
007F FFCCh
FLASH
Flash P/E status register
FPESTAT
16
2 to 3 PCLK
*7
007F FFCEh
FLASH
Data flash blank check status register
DFLBCSTAT
16
2 to 3 PCLK
*7
007F FFE8h
FLASH
Peripheral clock notification register
PCKAR
16
2 to 3 PCLK
*7
Notes:
1.
When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH
address is 000881ECh. When different output triggers are specified, the PPG0.NDRH addresses for pulse output groups
2 and 3 are 000881EEh and 000881ECh, respectively.
2.
When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL
address is 000881EDh. When different output triggers are specified, the PPG0.NDRL addresses for pulse output groups
0 and 1 are 000881EFh and 000881EDh, respectively.
3.
When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH
address is 000881FCh. When different output triggers are specified, the PPG1.NDRH addresses for pulse output groups
6 and 7 are 000881FEh and 000881FCh, respectively.
4.
When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL
address is 000881FDh. When different output triggers are specified, the PPG1.NDRL addresses for pulse output groups
4 and 5 are 000881FFh and 000881FDh, respectively.
5.
16-bit access to odd addresses is proh bited. When 16-bit access is required, access is at the address corresponding to
TMR0 or TMR2.
6.
For certain bits, functions differ according to whether the mode is serial communications or smart card interface.
7.
The number of access cycles varies depending on the number of divided cycles for clock synchronization (0 to one
PCLK).
8.
The number of access cycles may be 5 ICLK if the register is accessed during the DMAC operation.
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