R5F61634N50FPV PDF资料下载(370/1108 页)32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP120

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型号：	R5F61634N50FPV
元件分类：	微控制器/微处理器
英文描述：	32-BIT, FLASH, 50 MHz, MICROCONTROLLER, PQFP120
封装：	14 X 14 MM, 0.40 MM PITCH, LEAD FREE, PLASTIC, LQFP-120
文件页数：	370/1108页
文件大小：	6716K
代理商：	R5F61634N50FPV

DMA Controller (DMAC)

Rev. 1.00 Sep. 13, 2007 Page 305 of 1076

REJ09B0364-0100

Offset Subtraction

When setting the negative value in DOFR, the offset value must be 2's complement. The 2's

complement is obtained by the following formula.

2's complement of offset = 1 + ~offset (~: bit inversion)

2's complement of H'0001FFFF

= H'FFFE0000 + H'00000001

= H'FFFE0001

The value of 2's complement can be obtained by the NEG.L instruction.

Register during DMA Transfer

The DMAC registers are updated by a DMA transfer. The value to be updated differs according to

the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits

BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR.

DMA Source Address Register

When the transfer source address set in DSAR is accessed, the contents of DSAR are output and

then are updated to the next address.

The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and

SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the

offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11,

the address is decremented. The size of increment or decrement depends on the data access size.

The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0

= B'00, the data access size is byte and the address is incremented or decremented by 1. When

DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or

decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the

address is incremented or decremented by 4. Even if the access data size of the source address is

word or longword, when the source address is not aligned with the word or longword boundary,

the read bus cycle is divided into byte or word cycles. While data of one word or one longword is

being read, the size of increment or decrement is changing according to the actual data access size,

for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the

address when the read cycle is started is incremented or decremented by the value according to

bits SAT1 and SAT0.

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