- 您现在的位置：买卖IC网 > PDF目录69317 > R5F6461ELFP 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 PDF资料下载
参数资料
| 型号： | R5F6461ELFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 36/72页 |
| 文件大小： | 839K |
| 代理商： | R5F6461ELFP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页当前第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页
41
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
22.
TWI – Two-Wire Interface
22.1
Features
Two Identical two-wire interface peripherals
Bidirectional, two-wire communication interface
Phillips I2C compatible
System Management Bus (SMBus) compatible
Bus master and slave operation supported
Slave operation
Single bus master operation
Bus master in multi-master bus environment
Multi-master arbitration
Flexible slave address match functions
7-bit and general call address recognition in hardware
10-bit addressing supported
Address mask register for dual address match or address range masking
Optional software address recognition for unlimited number of addresses
Slave can operate in all sleep modes, including power-down
Slave address match can wake device from all sleep modes
100kHz and 400kHz bus frequency support
Slew-rate limited output drivers
Input filter for bus noise and spike suppression
Support arbitration between start/repeated start and data bit (SMBus)
Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2
Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.
相关PDF资料 |
PDF描述 |
|---|---|
| R5F71253N50NP | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQCC64 |
| R5F71252D50FA | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP64 |
| R5F71241N50NP | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQCC52 |
| R5F71252D50FA | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP64 |
| R5F71241D50FP | 32-BIT, FLASH, 50 MHz, RISC MICROCONTROLLER, PQFP48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| R5F70834RD80FTV | 制造商:Renesas Electronics Corporation 功能描述: |
| R5F70835AN80FTV | 制造商:Renesas Electronics Corporation 功能描述:Microcontroller,SH7083,ROM512K |
| R5F70845AN80FPV | 制造商:Renesas Electronics Corporation 功能描述:Microcontroller,SH7084,ROM512K |
| R5F70854AD80FPV | 制造商:Renesas Electronics Corporation 功能描述:Micro,SH-2,FL 256K,RAM16k,80MH |
| R5F70854AN80FPV | 制造商:Renesas Electronics Corporation 功能描述:Micro,SH-2,FL 256K,RAM16k,80MH |
发布紧急采购，3分钟左右您将得到回复。