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参数资料
| 型号： | R5F6461ELFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 48 MHz, MICROCONTROLLER, PQFP80 |
| 封装： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件页数： | 43/72页 |
| 文件大小： | 839K |
| 代理商： | R5F6461ELFP |
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48
XMEGA A3U [DATASHEET]
Atmel-8386D-AVR-ATxmega64A3U-128A3U-192A3U-256A3U–03/2014
29.
DAC – 12-bit Digital to Analog Converter
29.1
Features
One Digital to Analog Converter (DAC)
12-bit resolution
Two independent, continuous-drive output channels
Up to one million samples per second conversion rate per DAC channel
Built-in calibration that removes:
Offset error
Gain error
Multiple conversion trigger sources
On new available data
Events from the event system
High drive capabilities and support for
Resistive loads
Capacitive loads
Combined resistive and capacitive loads
Internal and external reference options
DAC output available as input to analog comparator and ADC
Low-power mode, with reduced drive strength
Optional DMA transfer of data
29.2
Overview
The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit
resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in
calibration system can remove offset and gain error when loaded with calibration values from software.
Figure 29-1. DAC overview.
A DAC conversion is automatically started when new data to be converted are available. Events from the event system
can also be used to trigger a conversion, and this enables synchronized and timed conversions between the DAC and
other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.
DAC0
DAC1
CTRLA
CH1DATA
CH0DATA
Trigger
Internal Output
enable
Enable
Internal 1.00V
AREFA
AREFB
Reference
selection
AVCC
Output
Driver
Output
Driver
D
A
T
A
Int.
driver
D
A
T
A
CTRLB
DMA req
(Data Empty)
DMA req
(Data Empty)
Select
12
Select
Enable
To
AC/ADC
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