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参数资料
| 型号： | R5F71474AK64FPV |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件页数： | 12/123页 |
| 文件大小： | 6757K |
| 代理商： | R5F71474AK64FPV |
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177
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
21. USI – Universal Serial Interface
21.1
Features
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
21.2
Overview
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication.
Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code
space than solutions based on software only. Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown in Figure 22-1 on page 188. For the actual placement of I/O pins,
refer to ”Pin configurations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in
bold. The device-specific I/O Register and bit locations are listed in the ”Register descriptions” on page 184.
Figure 21-1. Universal Serial Interface, block diagram.
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and outgoing data. The
register has no buffering so the data must be read as quickly as possible to ensure that no data is lost. The most
significant bit is connected to one of two output pins depending of the wire mode configuration. A transparent latch
is inserted between the Serial Register Output and output pin, which delays the change of data output to the oppo-
site clock edge of the data input sampling. The serial input is always sampled from the Data Input (DI) pin
independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow interrupt. Both the
Serial Register and the counter are clocked simultaneously by the same clock source. This allows the counter to
count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that
DATA
BUS
USIPF
USITC
USICLK
USICS0
USICS1
USIOIF
USIOIE
USIDC
USISIF
USIWM0
USIWM1
USISIE
Bit7
Two-wire Clock
Control Unit
DO
(Output only)
DI/SDA
(Input/Open Drain)
USCK/SCL
(Input/Open Drain)
4-bit Counter
USIDR
USISR
DQ
LE
USICR
CLOCK
HOLD
TIM0 COMP
Bit0
[1]
3
0
1
2
3
0
1
2
0
1
2
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